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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 20:
(3 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/52800/comment/848b8123_7ea8d7e5
PS20, Line 98: int enable_me(void)
blank line after previous function's ending `}`
https://review.coreboot.org/c/coreboot/+/52800/comment/3e2f77d7_ecc5347a
PS20, Line 103: struct enable_command {
: struct mkhi_hdr hdr;
: } __packed;
what is there to pack ?
https://review.coreboot.org/c/coreboot/+/52800/comment/5af32d9a_024de67b
PS20, Line 871: #if CONFIG(ME_STATE_BY_CMOS)
> > Have you seen the output of running: grep -r "if CONFIG" src/* […]
`if (CONFIG(ME_STATE_BY_CMOS))`
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Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
......................................................................
soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
This change adds S0ix device specific method _DSM ( UUID:
57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in.
Alone with this change, two kernel changes are also required:
https://chromium-review.googlesource.com/2800280https://chromium-review.googlesource.com/2800281
Once done, substate_requirement_registers is created under
/sys/kernel/debug/pmc_core/
Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to
check the content.
BUG=b:185437326
brya: _DSM method need to implemented in coreboot for PMC requirement
register.
Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/acpi/acpi/pep.asl
3 files changed, 37 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/5
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Change subject: ec: Add Star Labs ITE 8987E support
......................................................................
Patch Set 12: Code-Review+1
(4 comments)
File src/ec/starlabs/it8987/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/52797/comment/7f6aaf0e_d35fd7f9
PS12, Line 77: // Support DPTF feature
If you want to add DPTF support, it should be pretty easy, using the `drivers/intel/dptf` chip driver (see https://doc.coreboot.org/drivers/dptf.html)
https://review.coreboot.org/c/coreboot/+/52797/comment/a732974b_f748ea9c
PS12, Line 373:
: // Method(_Q45) // SMM Mode - Not used in coreboot
: // {
: // SMB2 = 0xC1
: // }
remove?
File src/ec/starlabs/it8987/acpi/hid.asl:
PS12:
just in general, why keep all of these commented-out lines?
https://review.coreboot.org/c/coreboot/+/52797/comment/b72728ff_e993d9dd
PS12, Line 16: // If (((OSYS >= 0x07DD) && (HEFE == One)))
remove?
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Change subject: mb/google/guybrush: Add helpers for cbi fw_config settings.
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/guybrush/variants/guybrush/helpers.c:
https://review.coreboot.org/c/coreboot/+/54639/comment/d6f50746_211d7270
PS4, Line 44: get_variant_wwan_type
> My counter proposal to your change is this:
Can you please expand on this a bit more with some examples?
> Each variant still supplies the option bit definitions as we do now.
Is this only for the fw_config fields that are applicable to the variant.
> All fw_config settings are defined in devicetree at a platform level - not about which bits are used for the settings, just having a definition so that it can be accessed by all variants.
Can you please provide more details of what this would look like? What changes are expected in the fw_config syntax as it currently exists in the devicetree and what it translates to as part of static.c or fw_config.c. Some examples would be helpful in understanding the proposal.
> The top level helpers can just check fw_config for anything they need to, and it's expected that they'd get back a response. If the config option doesn't exist on that platform, it's just returned as it's not enabled.
Can you please provide an example what the helper would really look like and what you mean by "get back a response"? What support would be required to determine config option doesn't exist on the platform.
> What I've proposed above doesn't require that we throw away all of the experience we have about this right now - it's an almost trivial expansion on what we already have.
It isn't really clear what the devicetree/static.c/fw_config.c/helpers would look like in this proposal. Can you please provide more details? I am all ears to understand the proposal.
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Change subject: src/mainboard: Add Star Labs labtop series
......................................................................
Patch Set 6: Code-Review+1
(10 comments)
Patchset:
PS6:
Suggestion: If you're willing, add yourself into the MAINTAINERS file with an entry for the StarLabs mainboards
Overall, looks pretty good, thanks Sean!
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/55128/comment/79ab6c1e_a9b4b2eb
PS6, Line 11: ### Purism
:
: [Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
: security; part of that effort is to minimize the amount of proprietary and/or
: binary code. Their laptops ship with a blob-free OS and coreboot firmware
: with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
Does this belong with this commit?
File src/mainboard/starlabs/labtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/55128/comment/87c34482_f2d62faa
PS6, Line 26: # select HAVE_IFD_BIN
: # select HAVE_ME_BIN
Why commented out?
https://review.coreboot.org/c/coreboot/+/55128/comment/b2c72cb8_d735b266
PS6, Line 89:
: config IFD_BIN_PATH
: string
: default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_0_flashdescriptor.bin"
you have HAVE_IFD_BIN commented out, so this doesn't apply
https://review.coreboot.org/c/coreboot/+/55128/comment/aedd7d32_fbccb74a
PS6, Line 94: config ME_BIN_PATH
: string
: default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashregion_2_intel_me.bin"
You have HAVE_ME_BIN commented out, so this doesn't apply
https://review.coreboot.org/c/coreboot/+/55128/comment/d0e12492_ce866a04
PS6, Line 112: #config VGA_BIOS_FILE
: # string
: # default "pci8086,9b41.rom" if BOARD_STARLABS_LABTOP_CML
: # default "pci8086,5917.rom" if BOARD_STARLABS_LABTOP_KBL
leave this out instead of commented out?
File src/mainboard/starlabs/labtop/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/55128/comment/5e9f1daa_4c4f6253
PS6, Line 54:
space
File src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex:
PS6:
Just curious, have you looked into util/spd_tools/ddr4?
File src/mainboard/starlabs/labtop/variants/cml/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/95c61a6b_a9ded5c3
PS6, Line 41: (gpio_get(GPP_H6) < 2) | (gpio_get(GPP_E23) < 1) | gpio_get(GPP_E22);
suggestion: use `gpio_base2_value` function, e.g.:
```
gpio_t memid_gpios[] = {
GPP_E22,
GPP_E23,
GPP_H6
};
return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios));
```
Also I think you mean
`gpio_get(GPP_H6) << 2`
etc., not
`gpio_get(GPP_H6) < 2`
File src/mainboard/starlabs/labtop/variants/kbl/romstage.c:
https://review.coreboot.org/c/coreboot/+/55128/comment/7c1dc5cc_e4099eca
PS6, Line 26: /* struct region_device spd_rdev; */
remove
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Change subject: mb/google/dedede/var/kracko: Add P-sensor support
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55133/comment/edef6857_0742faf2
PS1, Line 7: mb/google/dedede/var/kracko:Add P-sensor support
> Please add a space after the colon.
Done
https://review.coreboot.org/c/coreboot/+/55133/comment/4d74e983_6d4631d6
PS1, Line 10: would be fine tune later
> will be fine tuned later.
Done
Patchset:
PS3:
Thanks
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Hello build bot (Jenkins), Wisley Chen, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/kracko: Add P-sensor support
......................................................................
mb/google/dedede/var/kracko: Add P-sensor support
Configure GPIO D22/D23/E11.
Add P-sensor to device tree, register will be fine tune later.
BUG=b:178092096
BRANCH=dedede
TEST=built firmware and check ACPI table has P-sensor
Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/kracko/gpio.c
M src/mainboard/google/dedede/variants/kracko/overridetree.cb
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/55133/3
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Hello build bot (Jenkins), Wisley Chen, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55133
to look at the new patch set (#2).
Change subject: mb/google/dedede/var/kracko:i Add P-sensor support
......................................................................
mb/google/dedede/var/kracko:i Add P-sensor support
Configure GPIO D22/D23/E11.
Add P-sensor to device tree, register will be fine tune later.
BUG=b:178092096
BRANCH=dedede
TEST=built firmware and check ACPI table has P-sensor
Change-Id: I2c8feedd6efc1a471304322a17480c836e22349e
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/kracko/gpio.c
M src/mainboard/google/dedede/variants/kracko/overridetree.cb
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/55133/2
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