coreboot-gerrit June 2021

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Change in coreboot[master]: mb/google/brya: move MIPI camera setting into overridetree
by Furquan Shaikh (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak, Scott Chao. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55134 ) Change subject: mb/google/brya: move MIPI camera setting into overridetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Gerrit-Change-Number: 55134 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 01:37:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55151 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP This is to enable S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, one coreboot and two kernel changes are also required: https://review.coreboot.org/c/coreboot/+/55127 https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I87fa55e4003e789d55ddce11d1f76e9ca8b08f18 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55151/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87fa55e4003e789d55ddce11d1f76e9ca8b08f18 Gerrit-Change-Number: 55151 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Benjamin Doron (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Martin Roth, Matt DeVillier. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Maybe add that it substantially increases the final payload size? As I recall, it's some 300 KB larger with the debug messages. -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 01:10:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: move MIPI camera setting into overridetree
by Scott Chao (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55134 ) Change subject: mb/google/brya: move MIPI camera setting into overridetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55134/comment/cd3a97de_743f4751 PS1, Line 132: device ref ipu on end > CB:55143 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e64d078a8e39732ad29443c3b09ca008a7e902f Gerrit-Change-Number: 55134 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 01:08:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55150 to look at the new patch set (#3). Change subject: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP This is to enable S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, one coreboot and two kernel changes are also required: https://review.coreboot.org/c/coreboot/+/55127 https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method needs to implemented in coreboot for PMC requirement register. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I127c695eed9e2842996381c7559695f289cf4585 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55150/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I127c695eed9e2842996381c7559695f289cf4585 Gerrit-Change-Number: 55150 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAY...
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55146 ) Change subject: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8 Gerrit-Change-Number: 55146 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 00:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Martin Roth, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55145 ) Change subject: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5fe46b629e5275da54a5e86465a68271110397b Gerrit-Change-Number: 55145 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 00:56:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Angel Pons (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Martin Roth, Matt DeVillier, Benjamin Doron. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 00:55:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55127 to look at the new patch set (#6). Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in This change adds S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, two kernel changes are also required: https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method needs to implemented in coreboot for PMC requirement register. Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 3 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55127/comment/c49a0647_613971c1 PS4, Line 9: ( UUID: > Please remove the space after (. Done https://review.coreboot.org/c/coreboot/+/55127/comment/c4857cf2_1467daf3 PS4, Line 22: need to implemented > needs to be implemented Done File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/82a61d0b_42363f6e PS4, Line 16: #define PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536 > I’d only use the first macro, and calculate the bit value from it. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 00:50:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021