coreboot-gerrit June 2021

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Change in coreboot[master]: soc/mediatek: Move the MT8192 SPM driver to common
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Rex-BC Chen. Rex-BC Chen has removed Hung-Te Lin from this change. ( https://review.coreboot.org/c/coreboot/+/55139 ) Change subject: soc/mediatek: Move the MT8192 SPM driver to common ...................................................................... Removed reviewer Hung-Te Lin. -- To view, visit https://review.coreboot.org/c/coreboot/+/55139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Gerrit-Change-Number: 55139 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek: Move the MT8192 SPM driver to common
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Rex-BC Chen. Rex-BC Chen has removed Xi Chen from this change. ( https://review.coreboot.org/c/coreboot/+/55139 ) Change subject: soc/mediatek: Move the MT8192 SPM driver to common ...................................................................... Removed reviewer Xi Chen. -- To view, visit https://review.coreboot.org/c/coreboot/+/55139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Gerrit-Change-Number: 55139 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek: Move the MT8192 SPM driver to common
by Rex-BC Chen (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Xi Chen, Rex-BC Chen. Rex-BC Chen has removed Yu-Ping Wu from this change. ( https://review.coreboot.org/c/coreboot/+/55139 ) Change subject: soc/mediatek: Move the MT8192 SPM driver to common ...................................................................... Removed reviewer Yu-Ping Wu. -- To view, visit https://review.coreboot.org/c/coreboot/+/55139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Gerrit-Change-Number: 55139 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/55127/comment/4cd94ea9_8c8ead6a PS4, Line 16: #define PEPD_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536 > Done Hi Paul, I need to change this back due to syntax error when doing calculation in Field(). -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 02:07:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Move the MT8192 SPM driver to common
by Hung-Te Lin (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Xi Chen, Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55139 ) Change subject: soc/mediatek: Move the MT8192 SPM driver to common ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/55139/comment/e542b239_0084630c PS1, Line 5: //#include <device/mmio.h> remove this https://review.coreboot.org/c/coreboot/+/55139/comment/9cab82ac_13169fd9 PS1, Line 9: //#include <soc/symbols.h> remove this -- To view, visit https://review.coreboot.org/c/coreboot/+/55139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Gerrit-Change-Number: 55139 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 03 Jun 2021 02:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Initialize SSPM
by Hung-Te Lin (Code Review) 03 Jun '21

03 Jun '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55051 ) Change subject: soc/mediatek: Initialize SSPM ...................................................................... soc/mediatek: Initialize SSPM Load SSPM firmware and boot up SSPM in ramstage. This adds 23ms to the boot time. TEST=Load SSPM blob ok, and we can see some logs of SSPM from AP. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55051 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 3 files changed, 11 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig index f9bf846..02f7c5a 100644 --- a/src/soc/mediatek/mt8195/Kconfig +++ b/src/soc/mediatek/mt8195/Kconfig @@ -25,6 +25,12 @@ help The file name of the MediaTek MCUPM firmware. +config SSPM_FIRMWARE + string + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + config FLASH_DUAL_READ bool default y diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 1f89a58..ae325d5 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -54,6 +54,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c +ramstage-y += ../common/sspm.c ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/ufs.c @@ -66,7 +67,8 @@ MT8195_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8195 mcu-firmware-files := \ - $(CONFIG_MCUPM_FIRMWARE) + $(CONFIG_MCUPM_FIRMWARE) \ + $(CONFIG_SSPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8195_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index 3ebf23d..f9f4f99 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -4,6 +4,7 @@ #include <soc/emi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/ufs.h> #include <symbols.h> @@ -16,6 +17,7 @@ { mtk_mmu_disable_l2c_sram(); mcupm_init(); + sspm_init(); ufs_disable_refclk(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b Gerrit-Change-Number: 55051 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sc7180: Add display support for mipi panels
by Julius Werner (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52662 ) Change subject: sc7180: Add display support for mipi panels ...................................................................... Patch Set 13: (32 comments) Patchset: PS13: Apologies for the long review delay, had a very busy couple of weeks. Please separate this patch out from the sc7280 patch train and upload it separately, it's not really related to the rest. File src/mainboard/google/trogdor/Kconfig: https://review.coreboot.org/c/coreboot/+/52662/comment/3763da62_88b5d4c4 PS13, Line 12: default y if BOARD_GOOGLE_HOMESTAR Please keep the `default n` line here for consistency (even though it's also implicit). File src/mainboard/google/trogdor/mainboard.c: https://review.coreboot.org/c/coreboot/+/52662/comment/ad7e632a_0ef9c6dc PS13, Line 81: lanes This needs to be pinfo->lanes, right? https://review.coreboot.org/c/coreboot/+/52662/comment/880a2caa_f6bc1c97 PS13, Line 86: } else When one side of the if-else uses curly braces, the other one must as well (even for a single statement). File src/soc/qualcomm/sc7180/display/dsi.c: https://review.coreboot.org/c/coreboot/+/52662/comment/d6cf9f94_5a08c20c PS13, Line 117: mdss_dsi_clock_config(); Can you remove this now that you're already doing it earlier? https://review.coreboot.org/c/coreboot/+/52662/comment/62047f23_d47280b1 PS13, Line 163: DSI_PCLK_ON I assume all these changes are safe for eDP? Did you test this on existing eDP devices? https://review.coreboot.org/c/coreboot/+/52662/comment/85e7fd26_099a6646 PS13, Line 175: setbits32(&dsi0->int_ctrl, DSI_CMD_MODE_DMA_DONE_MASK); Same as below for the clear, can't these all just be written at once? https://review.coreboot.org/c/coreboot/+/52662/comment/8e8f8111_fa6c4727 PS13, Line 201: 0x00000001 Just write 0x1 https://review.coreboot.org/c/coreboot/+/52662/comment/d3b1354f_aa26ce55 PS13, Line 223: int count) No need for the new line? https://review.coreboot.org/c/coreboot/+/52662/comment/0031112e_6626eccb PS13, Line 226: uint8_t pload[256]; Are we sure that it's a good idea to DMA straight out of a stack buffer here? What about caching? You're not doing any flushes or anything -- surely this DMA engine isn't cache-snooping when all the others on this system aren't? We already have an 8K _dma_coherent buffer for the QSPI that is mapped uncached, we should probably just reuse that for this (we are single threaded so we'll never run MIPI init and QSPI code at the same time). https://review.coreboot.org/c/coreboot/+/52662/comment/15d4c6ee_8f8ea7ca PS13, Line 235: /* Align pload at 8 byte boundary */ Just do this: uint64_t aligned8[256 / sizeof(uint64_t)]; uint8_t *pload = aligned8; https://review.coreboot.org/c/coreboot/+/52662/comment/da4741f0_73bf4ff4 PS13, Line 248: size = cm->size; Just do size = ALIGN_UP(cm->size, PAYLOAD_SIZE); I believe something like PAYLOAD_ALIGN or PAYLOAD_SIZE_ALIGN would be a better name for that? https://review.coreboot.org/c/coreboot/+/52662/comment/6d60c6c8_e5697a46 PS13, Line 255: off Just use `pload` here and get rid of `off` (after making sure pload is an aligned buffer like I mentioned above). https://review.coreboot.org/c/coreboot/+/52662/comment/317ffb4f_ee477310 PS13, Line 255: size Please assert(size < ...amount of bytes in pload array...) before doing the memcpy(). (Maybe add a named constant for that 256.) https://review.coreboot.org/c/coreboot/+/52662/comment/5e83ef84_e82c1fd9 PS13, Line 257: if (use_tpg == false) { Please don't implement code that will never run. Just get rid of this branch and the use_tpg variable, in your code the TPG always seems to be used. (I assume there is some good reason why we have to use it? The non-TPG code path looks a lot simpler...) https://review.coreboot.org/c/coreboot/+/52662/comment/904a334f_94fcceeb PS13, Line 264: ALIGN Please use ALIGN_UP() (same thing, but clearer what it does). https://review.coreboot.org/c/coreboot/+/52662/comment/fb13640c_318df323 PS13, Line 266: if (len > DMA_TPG_FIFO_LEN) { This seems like it should be an assert() or something? We should probably notice if a command is too long, not just silently skip it. https://review.coreboot.org/c/coreboot/+/52662/comment/646b0802_a7a198ed PS13, Line 281: wmb(); Our I/O accessors (e.g. write32()) have implicit memory barriers, you shouldn't need any extra here (counts for all this code). https://review.coreboot.org/c/coreboot/+/52662/comment/ce62364a_23f0a26b PS13, Line 307: mdelay Let's define the wait delay in microseconds, not milliseconds, so we can have finer control if necessary. Please also rename `wait` to something that clarifies the unit (e.g. `delay_us`). https://review.coreboot.org/c/coreboot/+/52662/comment/afa02f5b_09b2ee37 PS13, Line 311: cm++; Rather than doing this just use cmds[i] everywhere (one loop variable is easier to keep track of than two). https://review.coreboot.org/c/coreboot/+/52662/comment/4128931b_16a5402a PS13, Line 319: write32(&dsi0->int_ctrl,0x0); > space required after that ',' (ctx:VxV) Please fix all of these. https://review.coreboot.org/c/coreboot/+/52662/comment/4cf8b540_fe6b8481 PS13, Line 331: setbits32(&dsi0->int_ctrl, DSI_BTA_DONE_AK); Do these bits all need to be written individually? Can't you just setbits32(&dsi0->int_ctrl, DSI_CMD_MODE_DMA_DONE_AK | DSI_CMD_MODE_MDP_DONE_AK | ...); ? https://review.coreboot.org/c/coreboot/+/52662/comment/1b81bffa_77eeb8b9 PS13, Line 351: mdelay(500); This seems ridiculous -- surely the mode change doesn't take half a second? File src/soc/qualcomm/sc7180/display/panel_driver.c: https://review.coreboot.org/c/coreboot/+/52662/comment/1e331457_5f06f13e PS13, Line 9: #define PANEL_RESET_GPIO GPIO(3) This seems unused? https://review.coreboot.org/c/coreboot/+/52662/comment/e97d9553_9b6fd311 PS13, Line 40: 0x96 Since these are milliseconds, please write them in decimal (not hex) so they're easier to read. https://review.coreboot.org/c/coreboot/+/52662/comment/95c90c30_b557325d PS13, Line 46: rm nit: these are usually in capitals https://review.coreboot.org/c/coreboot/+/52662/comment/a1703c4d_9f6df9e5 PS13, Line 47: .framebuffer_bits_per_pixel = 32, This... https://review.coreboot.org/c/coreboot/+/52662/comment/0e09e5be_d5e370cd PS13, Line 50: .x_resolution = 1080, ...and this... https://review.coreboot.org/c/coreboot/+/52662/comment/58928ddc_2a0e03c3 PS13, Line 51: .y_resolution = 2248, ...and this... https://review.coreboot.org/c/coreboot/+/52662/comment/5f10ac9a_14a499d3 PS13, Line 52: .bytes_per_line = 4320, ...and this shouldn't be set here. Instead, you should call edid_set_framebuffer_bits_per_pixel() in get_panel_config() to compute them from the other values. https://review.coreboot.org/c/coreboot/+/52662/comment/03b0422d_b100baf2 PS13, Line 73: memcpy(pinfo, &panel_info, sizeof(struct panel_data)); Why not just return a pointer to the panel_info? File src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h: https://review.coreboot.org/c/coreboot/+/52662/comment/e4aa86d4_b3733c7a PS13, Line 19: uint32_t size; nit: more efficient struct packing would be `payload` first, then `size` and `wait`. -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 13 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 01:57:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by zanxi chen (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Paul Menzel, Tao Xia, Karthikeyan Ramasubramanian. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54249/comment/2e197266_a00e363b PS3, Line 15: audio codec RT5682: 385 kHz > Paul is asking what was the observed frequency before this patch is introduced. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 5 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Jun 2021 01:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by zanxi chen (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: Furquan Shaikh, zanxi chen, Henry Sun, Paul Menzel, Tao Xia, Karthikeyan Ramasubramanian. zanxi chen has uploaded a new patch set (#5) to the change originally created by Tao Xia. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (<400 kHz). Measured I2C frequency changes are just as below after tuning: touchpad: 434kHz ---> 391kHz touchpanel: 439kHz ---> 382kHz audio codec RT5682: 445kHz ---> 385kHz BUG=b:187555396 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400 kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 --- M src/mainboard/google/dedede/variants/blipper/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/54249/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 5 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Krystal Han <hanlijing(a)huaqin.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 03 Jun '21

03 Jun '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph. Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Balaji Manigandan, Bernardo Perez Priego, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55127 to look at the new patch set (#7). Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in This change adds S0ix device specific method _DSM (UUID: 57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in. Alone with this change, two kernel changes are also required: https://chromium-review.googlesource.com/2800280 https://chromium-review.googlesource.com/2800281 Once done, substate_requirement_registers is created under /sys/kernel/debug/pmc_core/ Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to check the content. BUG=b:185437326 brya: _DSM method needs to implemented in coreboot for PMC requirement register. Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/55127/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2021