Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55147 )
Change subject: mb/google/brya/brya0: Fix irq and CS lines for FPMCU
......................................................................
mb/google/brya/brya0: Fix irq and CS lines for FPMCU
The entries in the ACPI tables for the fingerprint module's SPI
configuration were incorrect.
1) The GPIO is routed to IOAPIC (and SCI), therefore in ACPI, it must be
described by Interrupt(), not GpioInt(0
2) The chip-select signal was selected as 1, not 0 `device spi 0/1 on`
BUG=b:181635081
TEST=verified in kernel logs:
localhost # ~ dmesg|egrep 'cros-ec-dev|cros-ec-spi'
[ 4.569412] cros-ec-dev cros-ec-dev.1.auto: CrOS Fingerprint MCU detected
[ 4.575303] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I9ef6c99f011969fc444e0c12b806529cb82bba3d
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/55147/1
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 452e1d8..c2ee0a2e 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -328,9 +328,9 @@
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
- register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_F15)"
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
- device spi 1 on end
+ device spi 0 on end
end # FPMCU
end
device ref pch_espi on
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Change subject: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD
......................................................................
Patch Set 1: Code-Review+2
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Change subject: payloads/tianocore: Restrict bootsplash option to UEFIPAYLOAD
......................................................................
Patch Set 1: Code-Review+2
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Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging
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Patch Set 1: Code-Review+2
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Change subject: intel/common/block: Move mainboard api to tcss common block
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54733/comment/6658639f_44966e55
PS7, Line 9: As per the comments in CB:54090 mainboard api
: mainboard_tcss_get_port_info() is simplified and moved
: to tcss common block code.
> This text should be 72 characters wide
Ack
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/54733/comment/a7319f4c_44e9252b
PS5, Line 372: const struct device_path conn_path[] = {
: {.type = DEVICE_PATH_GENERIC, .generic.id = port, .generic.subid = 0},
: };
: const struct device *conn = find_dev_nested_path(mux->link_list, conn_path,
: ARRAY_SIZE(conn_path));
> You can get rid of the two above sections and just add the PMC device into this list here: […]
Done
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/54733/comment/2b245821_7e87913c
PS7, Line 346: static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
> nit: place static variables first in the declaration order
Ack
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Change subject: intel/common/block: Move mainboard api to tcss common block
......................................................................
Patch Set 8:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54733/comment/f41b2e5d_d8ce0b25
PS7, Line 6:
: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block
> `intel/common/block` is enough of a prefix
Ack
File src/drivers/intel/pmc_mux/conn/chip.h:
https://review.coreboot.org/c/coreboot/+/54733/comment/3b5e8e41_684b72ac
PS7, Line 32:
> nit: line up with `const struct device... […]
Ack
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/54733/comment/d9790118_a412d4d6
PS5, Line 342: const struct device *get_pmc_mux(void)
: {
: const struct device *pmc;
: const struct device *mux;
:
: pmc = pcidev_path_on_root(PCH_DEVFN_PMC);
: if (!pmc || !pmc->link_list) {
: printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__);
: return NULL;
: }
:
: mux = pmc->link_list->children;
: return mux;
: }
> This function isn't required, it can be rolled up into the call to `find_dev_nested_path` below
Ack
https://review.coreboot.org/c/coreboot/+/54733/comment/c4f6cd1d_ab0e4b4c
PS5, Line 361:
: const struct device *mux = get_pmc_mux();
:
: if (!mux || !mux->link_list) {
: printk(BIOS_ERR, "%s: unable to find PMC mux device or its connector\n",
: __func__);
: return NULL;
: }
> same as above, this won't be required
Ack
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/54733/comment/4d63b1e9_48d7a0e7
PS7, Line 349:
> nit: extra blank line
Ack
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Change subject: payload/external/tianocore/Kconfig: Toggle default payload
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Thanks for reaching out. It works for the UP2.
this patch can probably be dropped then, since CB:54019 has been merged
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Change subject: mb/ocp/deltalake: Add VPD option to force memory training
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Patch Set 2: Code-Review+2
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55146 )
Change subject: drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD
......................................................................
drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOAD
Tianocore UEFIPAYLOAD now supports SMMSTORE V2, so enable it by default
Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/drivers/smmstore/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/55146/1
diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig
index ba8268e..13b7312 100644
--- a/src/drivers/smmstore/Kconfig
+++ b/src/drivers/smmstore/Kconfig
@@ -9,6 +9,7 @@
config SMMSTORE_V2
bool "Use version 2 of SMMSTORE API"
depends on SMMSTORE
+ default y if TIANOCORE_UEFIPAYLOAD
default n
help
Version 2 of SMMSTORE allows secure communication with SMM and
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