coreboot-gerrit May 2021

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Change in coreboot[master]: soc/mediatek/mt8195: configure DMA buffer in DRAM
by Hung-Te Lin (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: configure DMA buffer in DRAM ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54052/comment/6a0ac595_2d673058 PS4, Line 7: set dram dma property > configure DMA buffer in DRAM Ack https://review.coreboot.org/c/coreboot/+/54052/comment/e5cdc423_2007e4eb PS4, Line 9: dram dma > DRAM DMA Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 06:16:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
by Subrata Banik (Code Review) 12 May '21

12 May '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52947 ) Change subject: include/console: Rename and update POST_ENTRY_RAMSTAGE postcode ...................................................................... include/console: Rename and update POST_ENTRY_RAMSTAGE postcode Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/console/post_codes.h M src/lib/hardwaremain.c 2 files changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 9682e4d..9b2398c 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -112,6 +112,14 @@ #define POST_PRE_HARDWAREMAIN 0x6e /** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_HARDWAREMAIN 0x6f + +/** * \brief Before Device Probe * * Boot State Machine: bs_pre_device() @@ -196,14 +204,6 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Before calling FSP Notify before End of Firmware * * Going to call into FSP binary for Notify phase diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 895a942..cd4a57e 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -442,7 +442,7 @@ cbmem_initialize(); timestamp_add_now(TS_START_RAMSTAGE); - post_code(POST_ENTRY_RAMSTAGE); + post_code(POST_ENTRY_HARDWAREMAIN); /* Handoff sleep type from romstage. */ acpi_is_wakeup_s3(); -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 12 May '21

12 May '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... include/console: Fix duplicate entry of postcode 0x79 Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52895 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/c_start.S M src/include/console/post_codes.h 2 files changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 19532d8..f55ab6e 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -89,7 +89,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - post_code(POST_PRE_HARDWAREMAIN) /* post fe */ + post_code(POST_PRE_HARDWAREMAIN) /* post 6e */ andl $0xFFFFFFF0, %esp diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 677cd36..9682e4d 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -105,6 +105,13 @@ #define POST_ENABLING_CACHE 0x60 /** + * \brief Pre call to RAM stage main() + * + * POSTed right before RAM stage main() is called from c_start.S + */ +#define POST_PRE_HARDWAREMAIN 0x6e + +/** * \brief Before Device Probe * * Boot State Machine: bs_pre_device() @@ -175,13 +182,6 @@ #define POST_BS_WRITE_TABLES 0x79 /** - * \brief Pre call to RAM stage main() - * - * POSTed right before RAM stage main() is called from c_start.S - */ -#define POST_PRE_HARDWAREMAIN 0x79 - -/** * \brief Load Payload * * Boot State Machine: bs_payload_load() -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#71) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M README.md 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/71 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 71 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: configure DMA buffer in DRAM
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54052 to look at the new patch set (#5). Change subject: soc/mediatek/mt8195: configure DMA buffer in DRAM ...................................................................... soc/mediatek/mt8195: configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54052/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen. Yu-Ping Wu has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... Removed Code-Review+2 by Yu-Ping Wu <yupingso(a)google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: mb/google/cherry: Pass reset gpio parameter to BL31
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54013 ) Change subject: mb/google/cherry: Pass reset gpio parameter to BL31 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This patch depends on CB:53898 -- To view, visit https://review.coreboot.org/c/coreboot/+/54013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Gerrit-Change-Number: 54013 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 12 May 2021 06:08:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Hung-Te Lin (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54052/comment/d3fc97ca_2aad7c88 PS4, Line 7: set dram dma property configure DMA buffer in DRAM https://review.coreboot.org/c/coreboot/+/54052/comment/7af28145_7059738b PS4, Line 9: dram dma DRAM DMA -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 06:05:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 06:01:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54052/comment/0af2ab31_02a82a3d PS3, Line 30: romstage-y += ../common/mmu_operations.c mmu_operations.c > Put this after i2c. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 05:49:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021