coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/cannonlake: Provide RefreshWm for users to config
by Marx Wang (Code Review) 12 May '21

12 May '21

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54079 ) Change subject: soc/intel/cannonlake: Provide RefreshWm for users to config ...................................................................... soc/intel/cannonlake: Provide RefreshWm for users to config To mitigate Row Hammer vulnerability, we could set refresh water mark to low (0). branch=master BUG=none TEST=add RefreshWm=0 in devicetree and check if 0xfed14238 bits[15:8] are changed. Signed-off-by: Marx Wang <marx.wang(a)intel.com> Change-Id: Ic364df8b446f291f410e09825075f5b5251621ff --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/54079/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3c8a68b..e1e98dd 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -435,6 +435,14 @@ /* Disable CPU Turbo in IA32_MISC_ENABLE */ bool cpu_turbo_disable; + + /* + * Refresh watermark value: + * 1 : Default value in FSP, high refresh watermark. + * 0 : low watermark to mitigate Row Hammer vulnerability. + * + */ + uint8_t RefreshWm; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 2bb3024..3779cc7 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -151,6 +151,9 @@ /* Set HECI1 PCI BAR address */ m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS; + /* Set refresh watermark */ + m_cfg->RefreshWm = config->RefreshWm; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic364df8b446f291f410e09825075f5b5251621ff Gerrit-Change-Number: 54079 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54052/comment/0b6bcc82_e08874d7 PS3, Line 30: romstage-y += ../common/mmu_operations.c mmu_operations.c Put this after i2c.c? -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 04:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable SCP SRAM
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54014 ) Change subject: soc/mediatek/mt8195: Enable SCP SRAM ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Gerrit-Change-Number: 54014 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 04:30:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 12 May '21

12 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/3689eaef_3f58cb5c PS3, Line 14: Ambient > I only see the first two sensors in the EC code... […] I added these sensors based on Schematics. Yes, even I am seeing this on my system. I am checking with hardware team, is this sensor physically available or not on board, that might be one of the reason it's showing negative temp value. Thanks for finding this. -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 03:53:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/volteer: add specific wifi SAR for volta
by YH Lin (Code Review) 12 May '21

12 May '21

Attention is currently required from: Nick Vaccaro, Sheng-Liang Pan, YH Lin. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54051 ) Change subject: mb/google/volteer/var/volteer: add specific wifi SAR for volta ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I000aefca63346c70556688f232ca54360b3badef Gerrit-Change-Number: 54051 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 03:47:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Harshit Sharma (Code Review) 12 May '21

12 May '21

Attention is currently required from: Werner Zeh. Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54050 ) Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... Patch Set 3: (3 comments) File util/crossgcc/patches/gcc-11.1.0_asan_shadow_offset_callback.patch: PS1: > Werner, Harshit: I had to adapt the patch a bit to fit into the new GCC options handling scheme. […] Looks good to me. https://review.coreboot.org/c/coreboot/+/54050/comment/87289a46_5a7d025a PS1, Line 34: gcc/params.def | 6 ++++++ : gcc/params.h | 2 ++ : 3 files changed, 30 insertions(+), 7 deletions(-) Could you update this? The new patch only changes asan.c and params.opt. https://review.coreboot.org/c/coreboot/+/54050/comment/73451dd4_54b9697f PS1, Line 56: addr and add a space after addr? -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 12 May 2021 03:45:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: spd: Clean up SPD files for JSL/TGL platform
by EricR Lai (Code Review) 12 May '21

12 May '21

EricR Lai has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49338 ) Change subject: spd: Clean up SPD files for JSL/TGL platform ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a871981642485020adaeaafd062f718c636a708 Gerrit-Change-Number: 49338 Gerrit-PatchSet: 8 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/mancomb: Update HUB_RST_L setting in GPIO
by Ivy Jian (Code Review) 12 May '21

12 May '21

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54078 ) Change subject: mb/google/mancomb: Update HUB_RST_L setting in GPIO ...................................................................... mb/google/mancomb: Update HUB_RST_L setting in GPIO Configure USB HUB_RESET_L gpio to high. BUG=b:187485847 TEST=Build and boot from USB to OS, check the USB function. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/54078/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index f829117..5ccbc10 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -51,7 +51,7 @@ /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* HUB_RST_L */ - PAD_GPO(GPIO_24, LOW), + PAD_GPO(GPIO_24, HIGH), /* GPIO_25: Not available */ /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ PAD_GPO(GPIO_26, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/54078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a Gerrit-Change-Number: 54078 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: set dram dma property
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54052 to look at the new patch set (#3). Change subject: soc/mediatek/mt8195: set dram dma property ...................................................................... soc/mediatek/mt8195: set dram dma property Set dram dma to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/54052/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_...
by David Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Marco Chen, Karthik Ramasubramanian. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52851 ) Change subject: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIG ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/dedede/variants/magolor/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52851/comment/0d63df7e_37e32d6b PS6, Line 208: 10 > * partners mentioned that this panel is leveraged from other platform bound with touchscreen chip to […] Done. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 01:24:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021