coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_...
by David Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: David Wu, Furquan Shaikh, Henry Sun, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Henry Sun, Marco Chen, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52851 to look at the new patch set (#7). Change subject: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIG ...................................................................... mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIG Select touchscreen(s) based on touchscreen source provisioned in SSFC of CBI (higher 32 bits of FW_CONFIG in coreboot). The reason is to avoid to enable multiple touchscreen ICs with the same slave address. BUG=b:186609348 TEST=build and boot to OS. Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 39 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/52851/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: add qclib support
by Shelley Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50582 ) Change subject: sc7280: add qclib support ...................................................................... Patch Set 34: (1 comment) Patchset: PS34: The change just landed. Can you try rebasing your CLs and seeing if that fixes Jenkins? -- To view, visit https://review.coreboot.org/c/coreboot/+/50582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Gerrit-Change-Number: 50582 Gerrit-PatchSet: 34 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Comment-Date: Wed, 12 May 2021 01:19:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51028 ) Change subject: mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP ...................................................................... mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP ADL-M LP4 RVP has command mirror enabled and we need to fill correct value of this UPD to pass the MRC. Also, Value of TxDqDqsRetraining is set to 1 by default and we need to disable it for only ADL-M LP5 RVP. BUG=None BRANCH=None TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/intel/adlrvp/memory.c 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 204744f..29eb744 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -20,6 +20,8 @@ .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { .dq_pins_interleaved = false, }, @@ -76,6 +78,8 @@ .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, + .LpDdrDqDqsReTraining = 1, + .ect = true, /* Early Command Training */ .UserBd = BOARD_TYPE_MOBILE, @@ -134,6 +138,8 @@ .ect = false, /* Early Command Training */ + .LpDdrDqDqsReTraining = 1, + .UserBd = BOARD_TYPE_MOBILE, .lp5x_config = { @@ -156,6 +162,8 @@ .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { .dq_pins_interleaved = false, } @@ -214,6 +222,10 @@ .ect = true, /* Early Command Training */ + .CmdMirror = 0xCC, + + .LpDdrDqDqsReTraining = 1, + .UserBd = BOARD_TYPE_ULT_ULX, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/51028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1 Gerrit-Change-Number: 51028 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/boten: Probe and enable amplifier operation mode
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52319 ) Change subject: mb/google/dedede/var/boten: Probe and enable amplifier operation mode ...................................................................... mb/google/dedede/var/boten: Probe and enable amplifier operation mode Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=b:180570923 BRANCH=dedede TEST=ALC1015Q-VB drive speaker OK Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 16 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index f914b82..cfb440e 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -230,13 +230,19 @@ register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP L"" register "uid" = "0" - device i2c 28 on end + device i2c 28 on + probe AUDIO_AMP RT1015_I2C + probe AUDIO_AMP UNPROVISIONED + end end chip drivers/i2c/generic register "hid" = ""10EC1015"" register "desc" = ""Realtek SPK AMP R"" register "uid" = "1" - device i2c 29 on end + device i2c 29 on + probe AUDIO_AMP RT1015_I2C + probe AUDIO_AMP UNPROVISIONED + end end end # I2C 4 device pci 19.1 on @@ -293,6 +299,13 @@ device i2c 28 on end end end # I2C 5 - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on + chip drivers/generic/alc1015 + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on + probe AUDIO_AMP RT1015P_AUTO + end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/52319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf Gerrit-Change-Number: 52319 Gerrit-PatchSet: 8 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Add GPIO and SPD for pirika support
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52923 ) Change subject: mb/google/dedede: Add GPIO and SPD for pirika support ...................................................................... mb/google/dedede: Add GPIO and SPD for pirika support Add support for GPIO and SPD driver for pirika BUG=b:184157747 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- A src/mainboard/google/dedede/variants/pirika/Makefile.inc A src/mainboard/google/dedede/variants/pirika/gpio.c M src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc M src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt 5 files changed, 61 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Alex1 Kao: Looks good to me, but someone else must approve Kirk Wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/pirika/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/Makefile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/pirika/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/pirika/gpio.c b/src/mainboard/google/dedede/variants/pirika/gpio.c new file mode 100644 index 0000000..79646b5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/pirika/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + + /* C18 : AP_I2C_EMR_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19 : AP_I2C_EMR_SCL */ + PAD_NC(GPP_C19, NONE), + + /* D12 : WCAM_RST_L */ + PAD_NC(GPP_D12, NONE), + /* D13 : EN_PP3300_CAMERA */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14 : EN_PP1200_CAMERA */ + PAD_NC(GPP_D14, NONE), + /* D15 : UCAM_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + /* D21 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_D21, NONE), + + /* E2 : CLK_24M_WCAM */ + PAD_NC(GPP_E2, NONE), + /* E17 : HDMI_DDC_SCL */ + PAD_NC(GPP_E17, NONE), + + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc index b0ca222..315f10f 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.inc @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt index fa24790..d0b9209 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt index e4258b5..ae86d68 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt @@ -1,11 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. - -# Part Name +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/52923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Gerrit-Change-Number: 52923 Gerrit-PatchSet: 2 Gerrit-Owner: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54028 ) Change subject: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver ...................................................................... soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver This will change the names of the GPP bridges, but this ok since there is no hand written ASL that references these names. BUG=b:184766519 TEST=Boot picasso and dump ACPI Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028 Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/pci/pcie_gpp.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/pcie_gpp.c 3 files changed, 10 insertions(+), 192 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index a3ac1cf..a1cc3d2 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -59,10 +59,17 @@ .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; +static const unsigned short internal_pci_gpp_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, + PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, + 0 +}; + static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { .ops = &internal_pcie_gpp_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, + .devices = internal_pci_gpp_ids, }; static struct device_operations external_pcie_gpp_ops = { @@ -76,6 +83,7 @@ }; static const unsigned short external_pci_gpp_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, 0 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 55b38c0..5897c7c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -42,6 +42,7 @@ select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index eabaa77..c46135f 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -1,16 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <acpi/acpigen.h> -#include <acpi/acpigen_pci.h> -#include <arch/ioapic.h> -#include <assert.h> #include <amdblocks/amd_pci_util.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pciexp.h> -#include <device/pci_ids.h> #include <soc/pci_devs.h> -#include <stdio.h> /* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ const struct pci_routing_info pci_routing_table[] = { @@ -30,185 +21,3 @@ *entries = ARRAY_SIZE(pci_routing_table); return pci_routing_table; } - -static const char *pcie_gpp_acpi_name(const struct device *dev) -{ - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - switch (dev->path.pci.devfn) { - case PCIE_GPP_0_DEVFN: - return "PBR0"; - case PCIE_GPP_1_DEVFN: - return "PBR1"; - case PCIE_GPP_2_DEVFN: - return "PBR2"; - case PCIE_GPP_3_DEVFN: - return "PBR3"; - case PCIE_GPP_4_DEVFN: - return "PBR4"; - case PCIE_GPP_5_DEVFN: - return "PBR5"; - case PCIE_GPP_6_DEVFN: - return "PBR6"; - case PCIE_GPP_A_DEVFN: - return "PBRA"; - case PCIE_GPP_B_DEVFN: - return "PBRB"; - } - - return NULL; -} - -/* - * This function writes a PCI device with _ADR, _STA, and _PRT objects: - * Example: - * Scope (\_SB.PCI0) - * { - * Device (PBRA) - * { - * Name (_ADR, 0x0000000000080001) // _ADR: Address - * Method (_STA, 0, NotSerialized) // _STA: Status - * { - * Return (0x0F) - * } - * - * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - * { - * If (PICM) - * { - * Return (Package (0x04) - * { - * Package (0x04) - * { - * 0x0000FFFF, - * 0x00, - * 0x00, - * 0x00000034 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x01, - * 0x00, - * 0x00000035 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x02, - * 0x00, - * 0x00000036 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x03, - * 0x00, - * 0x00000037 - * } - * }) - * } - * Else - * { - * Return (Package (0x04) - * { - * Package (0x04) - * { - * 0x0000FFFF, - * 0x00, - * \_SB.INTE, - * 0x00000000 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x01, - * \_SB.INTF, - * 0x00000000 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x02, - * \_SB.INTG, - * 0x00000000 - * }, - * - * Package (0x04) - * { - * 0x0000FFFF, - * 0x03, - * \_SB.INTH, - * 0x00000000 - * } - * }) - * } - * } - * } - * } - */ -static void acpi_device_write_gpp_pci_dev(const struct device *dev) -{ - const char *scope = acpi_device_scope(dev); - const char *name = acpi_device_name(dev); - - assert(dev->path.type == DEVICE_PATH_PCI); - assert(name); - assert(scope); - - acpigen_write_scope(scope); - acpigen_write_device(name); - - acpigen_write_ADR_pci_device(dev); - acpigen_write_STA(acpi_device_status(dev)); - - acpigen_write_pci_GNB_PRT(dev); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ -} - - -static struct device_operations internal_pcie_gpp_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, - 0 -}; - -static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { - .ops = &internal_pcie_gpp_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, -}; - -static struct device_operations external_pcie_gpp_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .acpi_name = pcie_gpp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, -}; - -static const struct pci_driver external_pcie_gpp_driver __pci_driver = { - .ops = &external_pcie_gpp_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/54028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Gerrit-Change-Number: 54028 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54028 ) Change subject: soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3 Gerrit-Change-Number: 54028 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 12 May 2021 00:45:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/pci: Capitalize PCI ACPI names
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54027 ) Change subject: soc/amd/common/block/pci: Capitalize PCI ACPI names ...................................................................... soc/amd/common/block/pci: Capitalize PCI ACPI names Lowercase characters are not valid ACPI identifiers. BUG=b:184766519 TEST=Boot picasso to OS and verify ACPI errors are no longer printed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54027 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/common/block/pci/pcie_gpp.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 58c7761..a3ac1cf 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -22,7 +22,7 @@ return NULL; name = malloc(ACPI_NAME_BUFFER_SIZE); - snprintf(name, ACPI_NAME_BUFFER_SIZE, "GP%02x", dev->path.pci.devfn); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "GP%02X", dev->path.pci.devfn); name[4] = '\0'; return name; -- To view, visit https://review.coreboot.org/c/coreboot/+/54027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944 Gerrit-Change-Number: 54027 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd{common,cezanne}: Move pcie_gpp.c to common
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54026 ) Change subject: soc/amd{common,cezanne}: Move pcie_gpp.c to common ...................................................................... soc/amd{common,cezanne}: Move pcie_gpp.c to common Cezanne and Picasso can now use the same driver. BUG=b:184766519 TEST=Boot guybrush and dump ASL. Verified it didn't change. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/pci/Kconfig M src/soc/amd/common/block/pci/Makefile.inc R src/soc/amd/common/block/pci/pcie_gpp.c 5 files changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 51bc4bc..327ec12 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 7053960..4731dc5 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -39,7 +39,6 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c -ramstage-y += pcie_gpp.c ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig index 4af0aa0..302a6b8 100644 --- a/src/soc/amd/common/block/pci/Kconfig +++ b/src/soc/amd/common/block/pci/Kconfig @@ -10,3 +10,9 @@ help Selecting this option adds the AMD-common enable_pci_mmconf function to the build. + +config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER + bool + depends on SOC_AMD_COMMON_BLOCK_PCI + help + Select this option to use AMD common PCIe GPP driver. diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index 8c7a989..e013777 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += amd_pci_util.c ramstage-y += pci_routing_info.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c similarity index 100% rename from src/soc/amd/cezanne/pcie_gpp.c rename to src/soc/amd/common/block/pci/pcie_gpp.c -- To view, visit https://review.coreboot.org/c/coreboot/+/54026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a Gerrit-Change-Number: 54026 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Configure TCSS OC pins
by Furquan Shaikh (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54076 ) Change subject: mb/google/volteer: Configure TCSS OC pins ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54076/comment/9adc7c6e_cc134e55 PS3, Line 9: volteer Are all volteer variants using the same OC pins? -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 00:40:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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