coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
by Furquan Shaikh (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54075 ) Change subject: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/54075/comment/300d5a95_c5f15242 PS1, Line 275: config->tcss_ports[i].ocpin; nit: This probably fits on the previous line within the 96-column limit? -- To view, visit https://review.coreboot.org/c/coreboot/+/54075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Gerrit-Change-Number: 54075 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 12 May 2021 00:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54065 ) Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... Patch Set 4: (3 comments) Patchset: PS3: > Can we make the FspUsb. […] Would have to change all the related devicetree entries as well. There are a _lot_.. File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/b4feb2ba_ddc633a7 PS3, Line 42: #endif > I think you can delete everything below this line. done File src/vendorcode/amd/fsp/cezanne/FspUsb.h: https://review.coreboot.org/c/coreboot/+/54065/comment/2421f2b0_4edd1949 PS1, Line 44: compdstune > Can you maybe add some breadcrumbs on where to look for these parameters? Right now I have no idea w […] People who have to adjust the phys will know. According to our USB phy designers it's a non-user serviceable part ;-). You'd need a 10GHz scope (USB3 Gen 2) and test jigs to really tune the phys. -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 May 2021 00:31:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jason Glenesk <jason.glenesk(a)gmail.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/cezanne: adding support for the changed AMD FSP API for USB PHY
by Julian Schroeder (Code Review) 12 May '21

12 May '21

Attention is currently required from: Marshall Dawson, Julian Schroeder, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54065 to look at the new patch set (#4). Change subject: amd/cezanne: adding support for the changed AMD FSP API for USB PHY ...................................................................... amd/cezanne: adding support for the changed AMD FSP API for USB PHY The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c A src/vendorcode/amd/fsp/cezanne/FspUsb.h M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 5 files changed, 176 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/54065/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Gerrit-Change-Number: 54065 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/root_complex: generate DPTC ACPI method
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54074 ) Change subject: soc/amd/cezanne/root_complex: generate DPTC ACPI method ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/root_complex.c: https://review.coreboot.org/c/coreboot/+/54074/comment/954a17eb_8aa88de7 PS1, Line 204: /* TODO: The code assumes that if DPTC gets called the folowing object exists */ done -- To view, visit https://review.coreboot.org/c/coreboot/+/54074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Gerrit-Change-Number: 54074 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 11 May 2021 23:56:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: factor out acpigen_write_alib_dptc to common code
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54077 to look at the new patch set (#2). Change subject: soc/amd: factor out acpigen_write_alib_dptc to common code ...................................................................... soc/amd: factor out acpigen_write_alib_dptc to common code Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 4 files changed, 33 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/54077/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Gerrit-Change-Number: 54077 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne/root_complex: generate DPTC ACPI method
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54074 to look at the new patch set (#2). Change subject: soc/amd/cezanne/root_complex: generate DPTC ACPI method ...................................................................... soc/amd/cezanne/root_complex: generate DPTC ACPI method This adds support for convertible devices to support different maximum power and thermal configurations. The dynamic power and thermal configuration (DPTC) via ACPI ALIB calls allows to change the parameters during runtime. This code contains the assumption that \_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At the moment only chromeec declares EC0.TBMD, but it's also the only code that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to the common code directory, since it's currently unsure if we might need to configure more than those 4 parameters for Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/root_complex.c 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/54074/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Gerrit-Change-Number: 54074 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: factor out acpigen_write_alib_dptc to common code
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54077 ) Change subject: soc/amd: factor out acpigen_write_alib_dptc to common code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/acpi/alib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119069): https://review.coreboot.org/c/coreboot/+/54077/comment/4f5b06e8_4ba7a2be PS1, Line 28: /* TODO: The code assumes that if DPTC gets called the folowing object exists */ 'folowing' may be misspelled - perhaps 'following'? -- To view, visit https://review.coreboot.org/c/coreboot/+/54077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Gerrit-Change-Number: 54077 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 11 May 2021 23:53:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: factor out acpigen_write_alib_dptc to common code
by Felix Held (Code Review) 12 May '21

12 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54077 ) Change subject: soc/amd: factor out acpigen_write_alib_dptc to common code ...................................................................... soc/amd: factor out acpigen_write_alib_dptc to common code Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 4 files changed, 33 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/54077/1 diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 68f4473..f101680 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -195,29 +195,9 @@ config->sustained_power_limit_tablet_mode_mW, config->fast_ppt_limit_tablet_mode_mW, config->slow_ppt_limit_tablet_mode_mW); - /* Scope (\_SB) */ - acpigen_write_scope("\\_SB"); - /* Method(DPTC, 0, Serialized) */ - acpigen_write_method_serialized("DPTC", 0); - - /* TODO: The code assumes that if DPTC gets called the folowing object exists */ - /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); - - acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, - sizeof(tablet_mode_input)); - - /* Else */ - acpigen_write_else(); - - acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, - sizeof(default_input)); - - acpigen_pop_len(); /* Else */ - - acpigen_pop_len(); /* Method DPTC */ - acpigen_pop_len(); /* Scope \_SB */ + acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), + (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); } static void root_complex_fill_ssdt(const struct device *device) diff --git a/src/soc/amd/common/block/acpi/alib.c b/src/soc/amd/common/block/acpi/alib.c index 5e1e8fb..f379bb7 100644 --- a/src/soc/amd/common/block/acpi/alib.c +++ b/src/soc/amd/common/block/acpi/alib.c @@ -4,7 +4,7 @@ #include <amdblocks/alib.h> #include <types.h> -void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) +static void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) { /* Name (buf_name, Buffer(size) {...} */ acpigen_write_name(buf_name); @@ -15,3 +15,29 @@ acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); acpigen_emit_namestring(buf_name); } + +void acpigen_write_alib_dptc(uint8_t *default_param, size_t default_param_len, + uint8_t *tablet_param, size_t tablet_param_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Method(DPTC, 0, Serialized) */ + acpigen_write_method_serialized("DPTC", 0); + + /* TODO: The code assumes that if DPTC gets called the folowing object exists */ + /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); + + acpigen_dptc_call_alib("TABB", tablet_param, tablet_param_len); + + /* Else */ + acpigen_write_else(); + + acpigen_dptc_call_alib("DEFB", default_param, default_param_len); + + acpigen_pop_len(); /* Else */ + + acpigen_pop_len(); /* Method DPTC */ + acpigen_pop_len(); /* Scope \_SB */ +} diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index b9d34c5..61608d5 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,7 +21,8 @@ uint32_t value; } __packed; -void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size); +void acpigen_write_alib_dptc(uint8_t *default_param, size_t default_param_len, + uint8_t *tablet_param, size_t tablet_param_len); #endif /* !__ACPI__ */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 3517e3d..eee2036 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -193,28 +193,9 @@ config->sustained_power_limit_tablet_mode_mW, config->fast_ppt_limit_tablet_mode_mW, config->slow_ppt_limit_tablet_mode_mW); - /* Scope (\_SB) */ - acpigen_write_scope("\\_SB"); - /* Method(DPTC, 0, Serialized) */ - acpigen_write_method_serialized("DPTC", 0); - - /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); - - acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, - sizeof(tablet_mode_input)); - - /* Else */ - acpigen_write_else(); - - acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, - sizeof(default_input)); - - acpigen_pop_len(); /* Else */ - - acpigen_pop_len(); /* Method DPTC */ - acpigen_pop_len(); /* Scope \_SB */ + acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), + (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); } static void root_complex_fill_ssdt(const struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/54077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Gerrit-Change-Number: 54077 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Configure TCSS OC pins
by Nick Vaccaro (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54076 to look at the new patch set (#3). Change subject: mb/google/volteer: Configure TCSS OC pins ...................................................................... mb/google/volteer: Configure TCSS OC pins TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/54076/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Configure TCSS OC pins
by Nick Vaccaro (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54076 to look at the new patch set (#2). Change subject: mb/google/volteer: Configure TCSS OC pins ...................................................................... mb/google/volteer: Configure TCSS OC pins TCSS OC pins has not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/54076/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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2016

2015

2014

2013

coreboot-gerrit May 2021