coreboot-gerrit May 2021

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Change in coreboot[master]: tests: Enable config override for tests
by Jakub Czapiga (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Hello build bot (Jenkins), Patrick Georgi, Paul Fagerburg, Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52937 to look at the new patch set (#3). Change subject: tests: Enable config override for tests ...................................................................... tests: Enable config override for tests Some tests require to change kconfig symbols values to cover the code. This patch enables one to set these vaues using <test-name>-config variable. Example for integer values. timestamp-test-config += CONFIG_HAVE_MONOTONIC_TIMER=1 Example for string values. Notice escaped quotes. spd_cache-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"SPD_CACHE_FMAP_NAME\" Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 --- M tests/Makefile.inc 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/52937/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tests: code coverage improvements
by Jakub Czapiga (Code Review) 12 May '21

12 May '21

Attention is currently required from: Paul Fagerburg. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54072 ) Change subject: tests: code coverage improvements ...................................................................... Patch Set 1: (2 comments) File tests/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54072/comment/e225fee7_dd7fc5db PS1, Line 180: ifeq ($(COV),1) I *think* that you should set COV to 1 if coverage-report-tests is present in the $(MAKECMDGOALS). COV=1 should be required only for a single unit-test. Use of coverage-report-tests indicates that user wants to generate coverage report so this target should not require additional "confirmation". If you decide to change this, remember to change docs as well :) https://review.coreboot.org/c/coreboot/+/54072/comment/5004a6d3_88bae360 PS1, Line 181: coverage-report-tests: clean-coverage-report-tests target might be useful. It may be an alias for clean-unit-tests. -- To view, visit https://review.coreboot.org/c/coreboot/+/54072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a Gerrit-Change-Number: 54072 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 08:16:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Lance Zhao (Code Review) 12 May '21

12 May '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > It's in document BWG doc #541817 mentioned in bug description. Please quote the BWG doc# in commit or comments for reference purpose, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 6 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 08:14:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Disable CBFS MCACHE again
by Kangheui Won (Code Review) 12 May '21

12 May '21

Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53933 ) Change subject: soc/amd/picasso: Disable CBFS MCACHE again ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I don't know that this ever worked. […] At least when I worked on CB:49468 it worked. I'll dig in to this. -- To view, visit https://review.coreboot.org/c/coreboot/+/53933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce Gerrit-Change-Number: 53933 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 12 May 2021 08:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Attention is currently required from: Werner Zeh, Harshit Sharma. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54050 ) Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... Patch Set 4: (2 comments) File util/crossgcc/patches/gcc-11.1.0_asan_shadow_offset_callback.patch: https://review.coreboot.org/c/coreboot/+/54050/comment/9de4f26a_faf4f410 PS1, Line 34: gcc/params.def | 6 ++++++ : gcc/params.h | 2 ++ : 3 files changed, 30 insertions(+), 7 deletions(-) > Could you update this? The new patch only changes asan.c and params.opt. I simply removed the block, given that the diff is manually edited now. https://review.coreboot.org/c/coreboot/+/54050/comment/a0787997_9fcc2d1a PS1, Line 56: addr > and add a space after addr? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Wed, 12 May 2021 08:10:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Update gcc to 11.1
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, Harshit Sharma, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54050 to look at the new patch set (#4). Change subject: util/crossgcc: Update gcc to 11.1 ...................................................................... util/crossgcc: Update gcc to 11.1 Various fixes to gnat and the improved nds32 backend have been merged into gcc by now, so we don't need to carry those patches anymore. Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-11.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-11.1.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-11.1.0_gnat.patch R util/crossgcc/patches/gcc-11.1.0_libcpp.patch R util/crossgcc/patches/gcc-11.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-11.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 25 insertions(+), 21,485 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/54050/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Gerrit-Change-Number: 54050 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Arthur Heymans (Code Review) 12 May '21

12 May '21

Attention is currently required from: Christian Walter, Angel Pons, Kyösti Mälkki, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54010 ) Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... Patch Set 2: (3 comments) File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/54010/comment/9a2b6025_5b31bcc4 PS2, Line 17: > For consistency with the other definitions, could you please indent these with tabs? Done https://review.coreboot.org/c/coreboot/+/54010/comment/1aecd798_fb17d15e PS2, Line 18: > nit: the bitfield macros for the other MSRs have an additional space after `#define` Done https://review.coreboot.org/c/coreboot/+/54010/comment/1ebf1055_b6777fc0 PS2, Line 23: (1 << 32) > Isn't this shift undefined behavior? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 12 May 2021 08:08:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe
by Arthur Heymans (Code Review) 12 May '21

12 May '21

Attention is currently required from: Christian Walter, Arthur Heymans, Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Christian Walter, Angel Pons, Kyösti Mälkki, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54010 to look at the new patch set (#3). Change subject: cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe ...................................................................... cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/entry16.S M src/include/cpu/intel/msr.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/54010/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Gerrit-Change-Number: 54010 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Create chronicler variant
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53907 ) Change subject: mb/google/volteer: Create chronicler variant ...................................................................... mb/google/volteer: Create chronicler variant Create the chronicler variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:187318819 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_CHRONICLER Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53907 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h A src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h A src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc A src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/chronicler/overridetree.cb 8 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve Paul Fagerburg: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 291ffb8..2fec5be 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -108,6 +108,7 @@ default "Copano" if BOARD_GOOGLE_COPANO default "Collis" if BOARD_GOOGLE_COLLIS default "Volet" if BOARD_GOOGLE_VOLET + default "Chronicler" if BOARD_GOOGLE_CHRONICLER config MAX_CPUS int @@ -154,6 +155,7 @@ default "copano" if BOARD_GOOGLE_COPANO default "collis" if BOARD_GOOGLE_COLLIS default "volet" if BOARD_GOOGLE_VOLET + default "chronicler" if BOARD_GOOGLE_CHRONICLER config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 14062a9..f445b46 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -91,3 +91,7 @@ config BOARD_GOOGLE_VOLET bool "-> Volet" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_CHRONICLER + bool "-> Chronicler" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h b/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h b/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/53907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Gerrit-Change-Number: 53907 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52865 ) Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work due to the dependency on FSP-M PCIe configuration. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/early_gpio_m.c 1 file changed, 88 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 116d3c6..3b60e24 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -11,6 +11,94 @@ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* WWAN_PWR_EN */ PAD_CFG_GPO(GPP_A8, 1, DEEP), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; static const struct pad_config early_uart_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021