coreboot-gerrit May 2021

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Change in coreboot[master]: Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54035 ) Change subject: Doc/nb/intel/sandybridge: Fix up some typos and cosmetics ...................................................................... Doc/nb/intel/sandybridge: Fix up some typos and cosmetics Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/northbridge/intel/sandybridge/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_registers.md 3 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index c1d4b99..27fbb2cc2 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -4,6 +4,6 @@ ## Topics -- [Native Ram Initialization](nri.md) +- [Native RAM Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) - [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 812cd23..bf0b89f 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Inoffical) register documentation +## (Unoffical) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -83,7 +83,7 @@ > **Note:** This feature is available since coreboot 4.4 ### MRC cache -The name *MRC cache* might be missleading as in case of *Native ram init* +The name *MRC cache* might be misleading as in case of *Native RAM init* there's no MRC, but for historical reasons it's still named *MRC cache*. The MRC cache is part of flash memory that is writeable by coreboot. At the end of the boot process coreboot will write the RAM training results to diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 8f85629..aae1205 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1,9 +1,9 @@ -# Inoffical Documentation of Intel MCHBAR register space. +# Unofficial Documentation of Intel MCHBAR register space. The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device. This documentation is incomplete and might be incorrect. -Please handle with care ! +Please handle with care! **MCHBAR + 0x4** -- To view, visit https://review.coreboot.org/c/coreboot/+/54035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d Gerrit-Change-Number: 54035 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53901 ) Change subject: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting ...................................................................... mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting Disable HSBIAS sense setting. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Vitaly Rodionov: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index f0343cd..5007719 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -148,6 +148,7 @@ register "bias_lvls[2]" = "4" register "bias_lvls[3]" = "1" register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" device i2c 48 on end end end # - I2C 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/53901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Gerrit-Change-Number: 53901 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52981 ) Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional ...................................................................... drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional HSBIAS_SENSE_EN configures HSBIAS output current sense through the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce the potential pop noise during the headset plug out slowly. But on some platforms ESD voltage will affect it causing test to fail, especially with CTIA headset type. For different hardware setups, a designer might want to tweak default behavior. Signed-off-by: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/52981 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/i2c/cs42l42/chip.h M src/drivers/i2c/cs42l42/cs42l42.c 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/cs42l42/chip.h b/src/drivers/i2c/cs42l42/chip.h index 5be2e14..1adffe7 100644 --- a/src/drivers/i2c/cs42l42/chip.h +++ b/src/drivers/i2c/cs42l42/chip.h @@ -106,4 +106,14 @@ uint64_t bias_lvls[4]; /* headset bias ramp rate */ enum cs42l42_hs_bias_ramp_rate hs_bias_ramp_rate; + /* + * cirrus,hs-bias-sense-disable: This is boolean property. If present the + * HSBIAS sense is disabled. Configures HSBIAS output current sense through + * the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce + * the potential pop noise during the headset plug out slowly. But on some + * platforms ESD voltage will affect it causing test to fail, especially + * with CTIA headset type. For different hardware setups, a designer might + * want to tweak default behavior. + */ + bool hs_bias_sense_disable; }; diff --git a/src/drivers/i2c/cs42l42/cs42l42.c b/src/drivers/i2c/cs42l42/cs42l42.c index d2ff6df..a871cfc 100644 --- a/src/drivers/i2c/cs42l42/cs42l42.c +++ b/src/drivers/i2c/cs42l42/cs42l42.c @@ -87,6 +87,8 @@ acpi_dp_add_integer_array(dsd, "cirrus,bias-lvls", config->bias_lvls, 4); acpi_dp_add_integer(dsd, "cirrus,hs-bias-ramp-rate", config->hs_bias_ramp_rate); + if (config->hs_bias_sense_disable) + acpi_dp_add_integer(dsd, "cirrus,hs-bias-sense-disable", 1); /* Write Device Property Hierarchy */ acpi_dp_write(dsd); -- To view, visit https://review.coreboot.org/c/coreboot/+/52981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Gerrit-Change-Number: 52981 Gerrit-PatchSet: 7 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: change vpp_sel default mux for 4k support
by Yu-Ping Wu (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54082 ) Change subject: soc/mediatek/mt8195: change vpp_sel default mux for 4k support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Gerrit-Change-Number: 54082 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 07:55:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: change vpp_sel default mux for 4k support
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54082 ) Change subject: soc/mediatek/mt8195: change vpp_sel default mux for 4k support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54082/comment/ebe95208_04e61f41 PS1, Line 8: > a few words explaining what is vpp_sel and how that is related to 4k (video?) support? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/54082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Gerrit-Change-Number: 54082 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 07:49:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#73) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M README.md 4 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/73 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 73 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: change vpp_sel default mux for 4k support
by Rex-BC Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54082 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: change vpp_sel default mux for 4k support ...................................................................... soc/mediatek/mt8195: change vpp_sel default mux for 4k support vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source. 1. Change vpp_sel source to mainpll_d4 to run at 546MHz 2. Change ethdr_sel source to univpll_d6 to run at 416MHz Signed-off-by: Nancy Lin <nancy.lin(a)mediatek.com> Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 --- M src/soc/mediatek/mt8195/pll.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/54082/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Gerrit-Change-Number: 54082 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Kangheui Won (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53905 ) Change subject: psp_verstage: remove not-implemented files for cezanne ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/53905/comment/f0794e16_b429fd6e PS1, Line 17: ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) > i'm ok with creating a ticket and addressing it later. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/53905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Gerrit-Change-Number: 53905 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 May 2021 07:45:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Kangheui Won (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Kangheui Won. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53905 to look at the new patch set (#3). Change subject: psp_verstage: remove not-implemented files for cezanne ...................................................................... psp_verstage: remove not-implemented files for cezanne Cezanne PSP is missing implementations for some svc apis. Do not include files related to missing svc apis. This CL should be reverted after the cezanne PSP supports these functions. BUG=b:187906425 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b --- M src/soc/amd/common/psp_verstage/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/53905/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/53905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Gerrit-Change-Number: 53905 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation/releases: Add more details about release notes
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54032 ) Change subject: Documentation/releases: Add more details about release notes ...................................................................... Documentation/releases: Add more details about release notes There are some steps when updating the release notes that are easily missed (see: I missed them for 4.14), so document them. Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54032 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/releases/checklist.md 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 7e66c4d..50d99f6 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -59,8 +59,9 @@ - [ ] If there are any deprecations announced for the following release, make sure that a list of currently affected boards and chipsets is part of the release notes. -- [ ] Finalize release notes (as much as possible), without specifying - release commit ids. +- [ ] Finalize release notes as much as possible +- [ ] Prepare release notes template for following release +- [ ] Update `Documentation/releases/index.md` - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of boards supported by vboot. @@ -68,7 +69,7 @@ - [ ] Select a commit ID to base the release upon, announce to IRC, ask for testing. - [ ] Test the commit selected for release. -- [ ] Update release notes with actual commit id, push to repo. +- [ ] Submit release notes - [ ] Create new release notes doc template for the next version. - [ ] Fill in the release date, remove "Upcoming release" and other filler from the current release notes. -- To view, visit https://review.coreboot.org/c/coreboot/+/54032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96 Gerrit-Change-Number: 54032 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021