coreboot-gerrit May 2021

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 3: (26 comments) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/647161b6_0c31c287 PS3, Line 68: #define PCIE1_MEM_SIZE 0x1fd00000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/748d273b_12e81fb5 PS3, Line 69: #define PCIE_MEM_END 0x404fffff please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/1f34611c_34837b3f PS3, Line 72: #define PCIE_1_QMP_PHY 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/bb8d76ca_f4d40317 PS3, Line 76: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/30bc044e_5ba971f4 PS3, Line 18: #define DEV_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/57dd36c7_dc97a3e8 PS3, Line 19: #define CLASS_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/6ea3698a_f54c7a71 PS3, Line 20: #define HEADER_SZ 8 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/d2efe71b_8e193238 PS3, Line 21: #define VEND_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/c47b78df_bd81dc28 PS3, Line 25: #define PCIE_CLASS 0x0a please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/a4f62aa8_a57344ef PS3, Line 26: #define PCI_MAX_DEV_FN 0x100 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/7fb3e268_4f23efca PS3, Line 41: #define PCIE1_3x2_NUM_LANES 2 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/119c0440_48f13961 PS3, Line 57: #define PERST_DELAY_US 1000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/ebd54c68_3581b386 PS3, Line 58: #define PCIE_MAX_BARS 6 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/926ddbec_90a26083 PS3, Line 154: #define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/07f4acbb_5f735916 PS3, Line 155: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/6c7841d2_b5b20236 PS3, Line 156: #define PCE1_QPHY_TX0 0x01C0E200 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/cf7cd63d_453b6605 PS3, Line 157: #define PCE1_QPHY_RX0 0x01C0E400 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/9dcada9d_a58e70f9 PS3, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/5c898cd2_47044130 PS3, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/99d7a657_dea3efe6 PS3, Line 188: #define PCIE_DEV(_bus, _dev, _fn) (0x80000000 | \ Macros with complex values should be enclosed in parentheses File src/soc/qualcomm/sc7280/pcie_host.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/8a3ed71f_186a911f PS3, Line 303: pci_ep_cfg_info.config_base = (void*)PCIE1_GEN3x2_CONF; "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/fe2fcf71_36d65959 PS3, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/bcc6581f_b4b5b89b PS3, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/77acf95e_7571f1c3 PS3, Line 468: printk(BIOS_NOTICE,"pcie ep PERST desserted\n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/7127753f_bc64ff65 PS3, Line 773: if (vend_id == 0xffff || vend_id == 0x0000) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119134): https://review.coreboot.org/c/coreboot/+/53902/comment/30c66931_6b403093 PS3, Line 1140: if(!ret) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add GSI FW download support
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52371 ) Change subject: sc7280: Add GSI FW download support ...................................................................... Patch Set 8: (11 comments) File src/soc/qualcomm/sc7280/include/soc/qupv3_config.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/e1b15a8c_85bc69c0 PS8, Line 77: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/ab6c35bf_ac548e09 PS8, Line 79: uint32_t iram_dword1; /* word 1 of a single IRAM firmware entry */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/9ca81015_fccc0792 PS8, Line 83: { open brace '{' following struct go on the same line File src/soc/qualcomm/sc7280/qupv3_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/0802cc38_219b7519 PS8, Line 204: write32(&regs->gsi_periph_base_lsb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/f02b2502_6430c052 PS8, Line 205: write32(&regs->gsi_periph_base_msb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/1841e26e_c5be1bd7 PS8, Line 210: if (fwIep[i].offset < GSI_REG_BASE_SIZE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/bc6bd94e_17b63301 PS8, Line 221: memcpy((&regs->gsi_inst_ramn),(void *)fwIRam, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/aeba3ab4_0e898726 PS8, Line 223: setbits_le32(&regs->gsi_mcs_cfg, GSI_MCS_CFG_MCS_ENABLE_BMSK ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/c84266fb_8c252b4d PS8, Line 224: setbits_le32(&regs->gsi_cfg, GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK | GSI_CFG_GSI_ENABLE_BMSK); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/8684424c_eefddcea PS8, Line 226: write32(&regs->gsi_ee_n_scratch_0_addr,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119130): https://review.coreboot.org/c/coreboot/+/52371/comment/5c6235b3_94e4e455 PS8, Line 227: write32(&regs->ee_n_gsi_ee_generic_cmd,0x81); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/52371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Gerrit-Change-Number: 52371 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 11:15:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 35: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/679fdc99_dc653e48 PS35, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/c98cece0_13e75b73 PS35, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/e7436456_fd142c77 PS35, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/fd5d9775_af4e100d PS35, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/09f2d068_692a784b PS35, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/d3c775db_1741315f PS35, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/d020b2c0_af31d750 PS35, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/c08f8e7a_3383291b PS35, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/46210e20_0e69704a PS35, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/236429e3_9678e3a6 PS35, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/4d482615_bcb7a050 PS35, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/b54dab2b_13ee6278 PS35, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/fbef7fdd_ed0c2046 PS35, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/bbf44ab1_7461623e PS35, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/e581e07c_3e1d1a55 PS35, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/95a8ba50_f312b015 PS35, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/2f3c3550_da0ad769 PS35, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/55382636_5d44e3ed PS35, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/abcd3fa9_031b1e32 PS35, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/3ffd6096_a78d557d PS35, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/7aa97012_ab78badf PS35, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/515b3dee_05f65845 PS35, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/5bfe7184_eb642c4d PS35, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/d3b9366a_5d49f65b PS35, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/6cb02e31_48503ab7 PS35, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/0fc6d9b2_32398c0a PS35, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/f0e71422_7eb6e60c PS35, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/b33d2f47_3a1fdc02 PS35, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/eb18d427_6892affc PS35, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/2897849b_7d3d9092 PS35, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/4bee438c_1812b991 PS35, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/65fc660c_f59f7214 PS35, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/db9c6ef3_3d4b82e3 PS35, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/920d7e6e_fe8e9fdb PS35, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/a6a9e977_619c7a11 PS35, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/52be1146_29446134 PS35, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/d4511b41_6ad1162b PS35, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/978a96b8_7d40d872 PS35, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/bd679f72_e3975670 PS35, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/08a5ce1d_5a939368 PS35, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/9028be1e_544212ca PS35, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119122): https://review.coreboot.org/c/coreboot/+/49768/comment/4997f02d_9bc0c6a9 PS35, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:13:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

1 0

Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 36: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119120): https://review.coreboot.org/c/coreboot/+/49392/comment/c6dbed2e_9139f0e6 PS36, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:12:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Paul Menzel, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... Patch Set 33: (4 comments) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119108): https://review.coreboot.org/c/coreboot/+/50587/comment/f94c7e01_fa934ad1 PS33, Line 16: REGION_SIZE(dram_wlan) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119108): https://review.coreboot.org/c/coreboot/+/50587/comment/ee3a697b_4dc10f62 PS33, Line 16: REGION_SIZE(dram_wlan) / KiB); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119108): https://review.coreboot.org/c/coreboot/+/50587/comment/ca12de4a_84b4fe85 PS33, Line 18: REGION_SIZE(dram_wpss) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119108): https://review.coreboot.org/c/coreboot/+/50587/comment/afe4ca1f_4bf86310 PS33, Line 18: REGION_SIZE(dram_wpss) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:02:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Ravi kumar (Code Review) 12 May '21

12 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sajida Bhanu, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50583 to look at the new patch set (#35). Change subject: herobrine: Enable macronix SPI config ...................................................................... herobrine: Enable macronix SPI config Enable macronix SPI config on herobrine board. Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/50583/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17
by Zhuohao Lee (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Hao Chou. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54085 ) Change subject: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Gerrit-Change-Number: 54085 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 10:46:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17
by Wayne3 Wang (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Hao Chou, Zhuohao Lee. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54085 ) Change subject: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Gerrit-Change-Number: 54085 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 10:45:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17
by Hao Chou (Code Review) 12 May '21

12 May '21

Attention is currently required from: Wayne3 Wang, Tim Wawrzynczak, Zhuohao Lee. Hao Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54085 ) Change subject: mb/google/volteer/variants/copano: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/54085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I428eb8db34c80d38899a2b823ec7193de4a8f5e4 Gerrit-Change-Number: 54085 Gerrit-PatchSet: 1 Gerrit-Owner: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 10:43:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021