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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54092 ) Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... Patch Set 1: (5 comments) File src/security/intel/txt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119156): https://review.coreboot.org/c/coreboot/+/54092/comment/03baae4a_b11ef7a4 PS1, Line 14: static const char *types[] = static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119156): https://review.coreboot.org/c/coreboot/+/54092/comment/d41b0c33_34a7b5bf PS1, Line 15: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119156): https://review.coreboot.org/c/coreboot/+/54092/comment/10173387_b5d6bae0 PS1, Line 33: static const char *unkown = "Unknown"; 'unkown' may be misspelled - perhaps 'unknown'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119156): https://review.coreboot.org/c/coreboot/+/54092/comment/fc0e6f85_94e03bcb PS1, Line 38: return unkown; 'unkown' may be misspelled - perhaps 'unknown'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119156): https://review.coreboot.org/c/coreboot/+/54092/comment/3e11e21a_e45758af PS1, Line 59: printk(BIOS_ERR, "%s\n", intel_txt_microcode_error_type(txt_error & TXT_ERROR_MASK)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 May 2021 14:23:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt: Add logging
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54093 ) Change subject: security/intel/cbnt: Add logging ...................................................................... Patch Set 1: (23 comments) File src/security/intel/cbnt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/d4b14be3_523bf998 PS1, Line 21: uint64_t : 24; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/4d1cfb91_f8a5f7ec PS1, Line 23: uint64_t : 1; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/a843171b_a868cb18 PS1, Line 25: uint64_t : 29; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/72aa8ed9_919812b5 PS1, Line 32: static const char *tpm_type[] = { static const char * array should probably be static const char * const Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/28d8485f_f63ed7de PS1, Line 41: uint64_t : 59; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/d70b38d4_60db9a88 PS1, Line 56: uint32_t : 15; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/d695f627_86d89856 PS1, Line 66: uint32_t : 5; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/934be21f_77b1c066 PS1, Line 73: _Static_assert(sizeof(union cbnt_errorcode) == sizeof(uint32_t), "Wrong size of cbnt_errorcode"); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/a0b1a9e7_7a060f29 PS1, Line 82: uint32_t : 2; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/6dfddadb_c23c3086 PS1, Line 93: uint32_t : 6; space prohibited before that ':' (ctx:WxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/3eb4bb02_3c32cf7b PS1, Line 111: return sinit_acm; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/b526cbe5_078be7ef PS1, Line 127: printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tTPM type:\t\t\t%s\n", tpm_type[acm_info.tpm_type]); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/1c4ca9bf_7aee36bd PS1, Line 129: printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tmeasured boot:\t\t\t%d\n", acm_info.measured_boot); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/c0ac7fe0_b4c252a2 PS1, Line 130: printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tverified boot:\t\t\t%d\n", acm_info.verified_boot); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/41c848ea_e8c7687c PS1, Line 138: printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tTXT disabled by policy:\t\t%d\n", btsts.txt_dis_pol); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/4bc76ca9_89621423 PS1, Line 139: printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tBootguard startup error:\t%d\n", btsts.btg_startup_err); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/86938d7a_e99276c4 PS1, Line 140: printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tTXT ucode or ACM error:\t\t%d\n", btsts.txt_err); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/80ff6e7a_e1ce1517 PS1, Line 156: printk(BIOS_DEBUG, "CBNT:\tERRORCODE: class:\t\t0x%x\n", err.sinit.class); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/bd036f7e_594d2a62 PS1, Line 167: const union cbnt_biosacm_errorcode biosacm_err = { .raw = read32((void *)CBNT_BIOSACM_ERRORCODE), }; line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/b240488b_97327c08 PS1, Line 175: printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: class:\t\t\t0x%x\n", biosacm_err.txt.class); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/c158a3cd_a135b756 PS1, Line 176: printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: major:\t\t\t0x%x\n", biosacm_err.txt.major); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/09bda215_73e2ee08 PS1, Line 192: printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: ACM started:\t\t\t%d\n", biosacm_err.btg.acm_started); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119157): https://review.coreboot.org/c/coreboot/+/54093/comment/f40681e2_df291644 PS1, Line 193: printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: KMID:\t\t\t0x%x\n", biosacm_err.btg.km_id); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Gerrit-Change-Number: 54093 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 12 May 2021 14:23:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt: Add logging
by Arthur Heymans (Code Review) 12 May '21

12 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54093 ) Change subject: security/intel/cbnt: Add logging ...................................................................... security/intel/cbnt: Add logging This decodes and logs the CBnT status and error registers. Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/cbnt/Kconfig M src/security/intel/cbnt/Makefile.inc A src/security/intel/cbnt/cbnt.h A src/security/intel/cbnt/logging.c M src/security/intel/txt/ramstage.c M src/soc/intel/xeon_sp/bootblock.c 6 files changed, 221 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/54093/1 diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig index a602cca..3d9fb49 100644 --- a/src/security/intel/cbnt/Kconfig +++ b/src/security/intel/cbnt/Kconfig @@ -17,6 +17,12 @@ if INTEL_CBNT_SUPPORT +config INTEL_CBNT_LOGGING + bool "Enable verbose CBnT logging" + help + Print more CBnT related debug output. + Use in pre-production environments only! + config INTEL_CBNT_GENERATE_KM bool "Generate Key Manifest (KM)" default y diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index c20a3dd..cdb8fa4 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) +all-$(CONFIG_INTEL_CBNT_LOGGING) += logging.c ramstage-y += cmos.c # The private key also contains the public key, so use that if a private key is provided. diff --git a/src/security/intel/cbnt/cbnt.h b/src/security/intel/cbnt/cbnt.h new file mode 100644 index 0000000..63433c3 --- /dev/null +++ b/src/security/intel/cbnt/cbnt.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define CBNT_BASE_ADDRESS 0xfed30000 + +#define CBNT_ERRORCODE (CBNT_BASE_ADDRESS + 0x30) +#define CBNT_BOOTSTATUS (CBNT_BASE_ADDRESS + 0xa0) +#define CBNT_BIOSACM_ERRORCODE (CBNT_BASE_ADDRESS + 0x328) + +void intel_cbnt_log_registers(void); diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c new file mode 100644 index 0000000..f358941 --- /dev/null +++ b/src/security/intel/cbnt/logging.c @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/msr.h> +#include <stdint.h> +#include <security/intel/txt/txt.h> + +#include "cbnt.h" + +union sacm_info { + struct { + uint64_t nem : 1; + uint64_t tpm_type : 2; + uint64_t tpm_succes : 1; + uint64_t reserved1 : 1; + uint64_t measured_boot : 1; + uint64_t verified_boot : 1; + uint64_t revoked : 1; + uint64_t : 24; + uint64_t btg_cap : 1; + uint64_t : 1; + uint64_t txt_cap : 1; + uint64_t : 29; + }; + uint64_t raw; +}; + +_Static_assert(sizeof(union sacm_info) == sizeof(uint64_t), "Wrong size of sacm_info"); + +static const char *tpm_type[] = { + "No TPM", + "TPM 1.2", + "TPM 2.0", + "PTT", +}; + +union cbnt_bootstatus { + struct { + uint64_t : 59; + uint64_t bios_trusted : 1; + uint64_t txt_dis_pol : 1; + uint64_t btg_startup_err : 1; + uint64_t txt_err : 1; + uint64_t type7 : 1; + }; + uint64_t raw; +}; +_Static_assert(sizeof(union cbnt_bootstatus) == sizeof(uint64_t), + "Wrong size of cbnt_bootstatus"); + +union cbnt_errorcode { + struct { + uint32_t type : 15; + uint32_t : 15; + uint32_t external : 1; + uint32_t valid : 1; + } microcode; + struct { + uint32_t ac_type : 4; + uint32_t class : 6; + uint32_t major : 5; + uint32_t minor_invalid : 1; + uint32_t minor : 9; + uint32_t : 5; + uint32_t external : 1; + uint32_t valid : 1; + } sinit; + uint32_t raw; +}; + +_Static_assert(sizeof(union cbnt_errorcode) == sizeof(uint32_t), "Wrong size of cbnt_errorcode"); + +union cbnt_biosacm_errorcode { + struct { + uint32_t ac_type : 4; + uint32_t class : 6; + uint32_t major : 5; + uint32_t minor_invalid : 1; + uint32_t minor : 12; + uint32_t : 2; + uint32_t external : 1; + uint32_t valid : 1; + } txt; + struct { + uint32_t ac_type : 4; + uint32_t class : 6; + uint32_t error : 5; + uint32_t acm_started : 1; + uint32_t km_id : 4; + uint32_t bp: 5; + uint32_t : 6; + uint32_t valid : 1; + } btg; + uint32_t raw; +}; +_Static_assert(sizeof(union cbnt_biosacm_errorcode) == sizeof(uint32_t), + "Wrong size of cbnt_biosacm_errorcode"); + + +static const char *decode_err_type(uint8_t type) +{ + static const char *bios_acm = "BIOS ACM Error", *sinit_acm = "SINIT ACM Error", + *btg = "Boot Guard Error", *reserved = "Reserved"; + + switch (type) { + case 0: + return bios_acm; + case 1: + return sinit_acm; + case 3: + return btg; + default: + return reserved; + } +} + +void intel_cbnt_log_registers(void) +{ + const msr_t sacm_info_msr = rdmsr(MSR_BOOT_GUARD_SACM_INFO); + const union sacm_info acm_info = { + .raw = sacm_info_msr.lo | ((uint64_t)sacm_info_msr.hi << 32) + }; + printk(BIOS_DEBUG, "CBNT:\tSACM INFO MSR (0x13A) raw: 0x%016llx\n", acm_info.raw); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tNEM status:\t\t\t%d\n", acm_info.nem); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tTPM type:\t\t\t%s\n", tpm_type[acm_info.tpm_type]); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tTPM succes:\t\t\t%d\n", acm_info.tpm_succes); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tmeasured boot:\t\t\t%d\n", acm_info.measured_boot); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tverified boot:\t\t\t%d\n", acm_info.verified_boot); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\trevoked:\t\t\t%d\n", acm_info.revoked); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tBtG capable:\t\t\t%d\n", acm_info.btg_cap); + printk(BIOS_DEBUG, "CBNT:\tSACM INFO:\tTXT capable:\t\t\t%d\n", acm_info.txt_cap); + + const union cbnt_bootstatus btsts = { .raw = read64((void *)CBNT_BOOTSTATUS), }; + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS (0xA0) raw: 0x%016llx\n", btsts.raw); + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tBios trusted:\t\t\t%d\n", btsts.bios_trusted); + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tTXT disabled by policy:\t\t%d\n", btsts.txt_dis_pol); + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tBootguard startup error:\t%d\n", btsts.btg_startup_err); + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tTXT ucode or ACM error:\t\t%d\n", btsts.txt_err); + printk(BIOS_DEBUG, "CBNT:\tBOOTSTATUS:\tTXT measurement type 7:\t\t%d\n", btsts.type7); + + const union cbnt_errorcode err = { .raw = read32((void *)CBNT_ERRORCODE), }; + printk(BIOS_DEBUG, "CBNT:\tERRORCODE (0x30) raw: 0x%08x\n", err.raw); + if (btsts.txt_err) { + if (!btsts.txt_dis_pol) { + if (err.microcode.valid && !err.microcode.external) { + printk(BIOS_DEBUG, "CBNT:\tERRORCODE is ucode error\n"); + printk(BIOS_DEBUG, "CBNT:\tERRORCODE: type:\t\t%s\n", + intel_txt_microcode_error_type(err.microcode.type)); + } else if (err.sinit.valid && err.sinit.external) { + printk(BIOS_DEBUG, "CBNT:\tERRORCODE is SINIT error\n"); + const char *type = decode_err_type(err.sinit.ac_type); + printk(BIOS_DEBUG, "CBNT:\tERRORCODE: AC Module Type:\t\t%s\n", + type); + printk(BIOS_DEBUG, "CBNT:\tERRORCODE: class:\t\t0x%x\n", err.sinit.class); + printk(BIOS_DEBUG, "CBNT:\tERRORCODE: major:\t\t0x%x\n", + err.sinit.major); + if (!err.sinit.minor_invalid) + printk(BIOS_DEBUG, + "CBNT:\tERRORCODE: minor:\t\t0x%x\n", + err.sinit.minor); + } + } + } + + const union cbnt_biosacm_errorcode biosacm_err = { .raw = read32((void *)CBNT_BIOSACM_ERRORCODE), }; + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE (0x328) raw: 0x%08x\n", biosacm_err.raw); + /* It looks like the hardware does not set the txt error bit properly */ + const bool txt_err_valid = btsts.txt_err || true; + if (txt_err_valid && biosacm_err.txt.valid) { + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: TXT ucode or ACM error\n"); + const char *type = decode_err_type(biosacm_err.txt.ac_type); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: AC Module Type:\t\t%s\n", type); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: class:\t\t\t0x%x\n", biosacm_err.txt.class); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: major:\t\t\t0x%x\n", biosacm_err.txt.major); + if (!biosacm_err.txt.minor_invalid) + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: minor:\t\t\t0x%x\n", + biosacm_err.txt.minor); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: External:\t\t\t0x%x\n", + biosacm_err.txt.external); + } + + if (btsts.btg_startup_err && biosacm_err.btg.valid) { + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: Bootguard error\n"); + const char *type = decode_err_type(biosacm_err.btg.ac_type); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: AC Module Type:\t\t%s\n", type); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: class:\t\t\t0x%x\n", + biosacm_err.btg.class); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: error:\t\t\t0x%x\n", + biosacm_err.btg.error); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: ACM started:\t\t\t%d\n", biosacm_err.btg.acm_started); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: KMID:\t\t\t0x%x\n", biosacm_err.btg.km_id); + printk(BIOS_DEBUG, "CBNT:\tBIOSACM_ERRORCODE: BootPolicies:\t\t\t0x%x\n", + biosacm_err.btg.bp); + } +} diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index c830f97..91d4efd 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -130,6 +130,9 @@ intel_txt_log_spad(); + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + if (CONFIG(INTEL_TXT_LOGGING)) { intel_txt_log_bios_acm_error(); txt_dump_chipset_info(); diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index baf5ab5..f4bdd09 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <intelblocks/lpc_lib.h> +#include <security/intel/cbnt/cbnt.h> #include <soc/pci_devs.h> #include <soc/bootblock.h> #include <fsp/util.h> @@ -70,5 +71,9 @@ if (CONFIG(FSP_CAR)) report_fspt_output(); + + if (CONFIG(INTEL_CBNT_SUPPORT)) + intel_cbnt_log_registers(); + bootblock_pch_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635 Gerrit-Change-Number: 54093 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by Arthur Heymans (Code Review) 12 May '21

12 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54092 ) Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... security/intel/txt: Split of microcode error type printing The purpose is to reuse the types string in CBnT error printing. Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/Makefile.inc M src/security/intel/txt/logging.c M src/security/intel/txt/txt.h 3 files changed, 34 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/54092/1 diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index d332341..5c3ddde 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_INTEL_TXT),y) +bootblock-y += logging.c + romstage-y += romstage.c romstage-y += getsec_sclean.S romstage-y += getsec.c diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 683247d..641288e 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -3,11 +3,41 @@ #include <arch/mmio.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <stdint.h> #include <types.h> #include "txt.h" #include "txt_register.h" +const char *intel_txt_microcode_error_type(uint8_t type) +{ + static const char *types[] = + { + "Legacy Shutdown", + "", + "", + "", + "", + "Load memory type error in ACM area", + "Unrecognized ACM format", + "Failure to authenticate", + "Invalid ACM format", + "Unexpected Snoop hit", + "Invalid event", + "Invalid MLE", + "Machine check event", + "VMXAbort", + "AC memory corruption", + "Illegal voltage/bus ratio", + }; + static const char *unkown = "Unknown"; + + if (type <= 15 && !(type > 0 && type < 5)) + return types[type]; + + return unkown; +} + /** * Logs microcode or SINIT ACM errors. * Does not log SBIOS ACM errors. @@ -26,47 +56,7 @@ printk(BIOS_ERR, " Type: "); - switch (txt_error & TXT_ERROR_MASK) { - case 0: - printk(BIOS_ERR, "Legacy Shutdown\n"); - break; - case 5: - printk(BIOS_ERR, "Load memory type error in ACM area\n"); - break; - case 6: - printk(BIOS_ERR, "Unrecognized ACM format\n"); - break; - case 7: - printk(BIOS_ERR, "Failure to authenticate\n"); - break; - case 8: - printk(BIOS_ERR, "Invalid ACM format\n"); - break; - case 9: - printk(BIOS_ERR, "Unexpected Snoop hit\n"); - break; - case 10: - printk(BIOS_ERR, "Invalid event\n"); - break; - case 11: - printk(BIOS_ERR, "Invalid MLE\n"); - break; - case 12: - printk(BIOS_ERR, "Machine check event\n"); - break; - case 13: - printk(BIOS_ERR, "VMXAbort\n"); - break; - case 14: - printk(BIOS_ERR, "AC memory corruption\n"); - break; - case 15: - printk(BIOS_ERR, "Illegal voltage/bus ratio\n"); - break; - default: - printk(BIOS_ERR, "unknown\n"); - break; - } + printk(BIOS_ERR, "%s\n", intel_txt_microcode_error_type(txt_error & TXT_ERROR_MASK)); } } diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h index 976cc74..60c2408 100644 --- a/src/security/intel/txt/txt.h +++ b/src/security/intel/txt/txt.h @@ -26,5 +26,6 @@ void intel_txt_run_sclean(void); int intel_txt_run_bios_acm(const u8 input_params); bool intel_txt_prepare_txt_env(void); +const char *intel_txt_microcode_error_type(uint8_t type); #endif /* SECURITY_INTEL_TXT_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Provide RefreshWm for users to configurate
by Marx Wang (Code Review) 12 May '21

12 May '21

Marx Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/54079 ) Change subject: soc/intel/cannonlake: Provide RefreshWm for users to configurate ...................................................................... Abandoned can't find the FspmUPD.h for CNL/CML. -- To view, visit https://review.coreboot.org/c/coreboot/+/54079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic364df8b446f291f410e09825075f5b5251621ff Gerrit-Change-Number: 54079 Gerrit-PatchSet: 5 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/intel/sm: Enable TCSS
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54091 ) Change subject: mb/intel/sm: Enable TCSS ...................................................................... mb/intel/sm: Enable TCSS Enable flag SOC_INTEL_COMMON_BLOCK_TCSS. Add 'mainboard_tcss_get_port_info' function similar to volteer. TEST=Verified build for shadowmountain Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: I8be796295a900bed58b5c7ed6c2300fe504d58a3 --- M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/shadowmountain/mainboard.c 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/54091/1 diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 94a279f..b66b054 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -25,6 +25,7 @@ select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BLOCK_TCSS config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c index 2783b4d..eca29b7 100644 --- a/src/mainboard/intel/shadowmountain/mainboard.c +++ b/src/mainboard/intel/shadowmountain/mainboard.c @@ -6,6 +6,68 @@ #include <ec/ec.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <intelblocks/tcss.h> +#include <soc/pci_devs.h> +#include "drivers/intel/pmc_mux/conn/chip.h" + +extern struct chip_operations drivers_intel_pmc_mux_conn_ops; + +static bool is_correct_port(const struct device *dev, int port) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port + && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static const struct drivers_intel_pmc_mux_conn_config *get_connector_config( + const struct device *mux, + int port) +{ + const struct drivers_intel_pmc_mux_conn_config *config = NULL; + DEVTREE_CONST struct device *conn = NULL; + + while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) { + if (is_correct_port(conn, port)) + break; + } + + if (conn) + config = (const struct drivers_intel_pmc_mux_conn_config *) conn->chip_info; + + return config; +} + +const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports) +{ + static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; + size_t port; + const struct device *pmc; + const struct device *mux; + const struct drivers_intel_pmc_mux_conn_config *mux_config; + size_t active_ports = 0; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return NULL; + } + + mux = pmc->link_list->children; + if (!mux) + return NULL; + + for (port = 0; port < MAX_TYPE_C_PORTS; port++) { + mux_config = get_connector_config(mux, port); + if (mux_config == NULL) + continue; + + port_map[active_ports].usb2_port = mux_config->usb2_port_number; + port_map[active_ports].usb3_port = mux_config->usb3_port_number; + active_ports++; + } + + *num_ports = active_ports; + return port_map; +} static void mainboard_init(void *chip_info) { -- To view, visit https://review.coreboot.org/c/coreboot/+/54091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be796295a900bed58b5c7ed6c2300fe504d58a3 Gerrit-Change-Number: 54091 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable TCSS
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak. Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54090 ) Change subject: mb/google/brya: Enable TCSS ...................................................................... mb/google/brya: Enable TCSS Enable flag SOC_INTEL_COMMON_BLOCK_TCSS. Add 'mainboard_tcss_get_port_info' function similar to volteer. TEST=Verified build for brya Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/mainboard.c 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/54090/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index a910cc7..93f854d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -24,6 +24,7 @@ select SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_COMMON_BLOCK_TCSS if BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 99a060d..09f9e25 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -5,6 +5,68 @@ #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <intelblocks/tcss.h> +#include <soc/pci_devs.h> +#include "drivers/intel/pmc_mux/conn/chip.h" + +extern struct chip_operations drivers_intel_pmc_mux_conn_ops; + +static bool is_correct_port(const struct device *dev, int port) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port + && dev->chip_ops == &drivers_intel_pmc_mux_conn_ops; +} + +static const struct drivers_intel_pmc_mux_conn_config *get_connector_config( + const struct device *mux, + int port) +{ + const struct drivers_intel_pmc_mux_conn_config *config = NULL; + DEVTREE_CONST struct device *conn = NULL; + + while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) { + if (is_correct_port(conn, port)) + break; + } + + if (conn) + config = (const struct drivers_intel_pmc_mux_conn_config *) conn->chip_info; + + return config; +} + +const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports) +{ + static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; + size_t port; + const struct device *pmc; + const struct device *mux; + const struct drivers_intel_pmc_mux_conn_config *mux_config; + size_t active_ports = 0; + + pmc = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!pmc || !pmc->link_list) { + printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); + return NULL; + } + + mux = pmc->link_list->children; + if (!mux) + return NULL; + + for (port = 0; port < MAX_TYPE_C_PORTS; port++) { + mux_config = get_connector_config(mux, port); + if (mux_config == NULL) + continue; + + port_map[active_ports].usb2_port = mux_config->usb2_port_number; + port_map[active_ports].usb3_port = mux_config->usb3_port_number; + active_ports++; + } + + *num_ports = active_ports; + return port_map; +} static void mainboard_init(void *chip_info) { -- To view, visit https://review.coreboot.org/c/coreboot/+/54090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Gerrit-Change-Number: 54090 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: mb/intel/sm: Add tcss code
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54089 ) Change subject: soc/intel/alderlake: mb/intel/sm: Add tcss code ...................................................................... soc/intel/alderlake: mb/intel/sm: Add tcss code Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/tcss.h 4 files changed, 35 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/54089/1 diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index beaf8fd..fea1c19 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -14,8 +14,7 @@ # TCSS register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x09020005" - register "IomTypeCPortPadCfg[1]" = "0x09020006" + register "typec_aux_bias_pads[0]" = "{.pullup = GPP_A5, .pulldown = GPP_A6}" # Enable heci communication register "HeciEnabled" = "1" diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index fb9dd73..57b7868 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -212,17 +212,14 @@ bool CnviBtAudioOffload; /* - * IOM Port Config - * If a port orientation needs to be controlled by the SOC this setting must be - * updated to reflect the correct GPIOs being used for the SOC port flipping. - * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down - * 0,1 are pull up and pull down for port 0 - * 2,3 are pull up and pull down for port 1 - * 4,5 are pull up and pull down for port 2 - * 6,7 are pull up and pull down for port 3 - * values to be programmed correspond to the GPIO family and offsets + * These GPIOs will be programmed by the IOM to handle biasing of the + * Type-C aux (SBU) signals when certain alternate modes are used. + * `pad_auxn_dc` should be assigned to the GPIO pad providing negative + * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, + * `pad_auxp_dc` should be assigned to the GPIO providing positive bias + * (name often contains `AUXP_DC` or `_AUX_P`). */ - uint32_t IomTypeCPortPadCfg[8]; + struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; /* * SOC Aux orientation override: diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2ab1825..8664fe6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -12,6 +12,7 @@ #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <intelblocks/mp_init.h> +#include <intelblocks/tcss.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -94,6 +95,7 @@ const struct microcode *microcode_file; size_t microcode_len; FSP_S_CONFIG *params = &supd->FspsConfig; + FSPS_ARCH_UPD *pfsps_arch_upd = &supd->FspsArchUpd; uint32_t enable_mask; struct device *dev; @@ -129,8 +131,9 @@ params->D3ColdEnable = !config->TcssD3ColdDisable; params->TcssAuxOri = config->TcssAuxOri; - for (i = 0; i < 8; i++) - params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i]; + + /* Explicitly clear this field to avoid using defaults */ + memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg)); /* * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will @@ -189,6 +192,9 @@ params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ + pfsps_arch_upd->EnableMultiPhaseSiliconInit = 1; + /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); if (dev) { @@ -298,11 +304,6 @@ mainboard_silicon_init_params(params); } -int soc_fsp_multi_phase_init_is_enable(void) -{ - return 0; -} - /* * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit * This platform supports below MultiPhaseSIInit Phase(s): @@ -315,6 +316,13 @@ switch (phase_index) { case 1: /* TCSS specific initialization here */ + printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", + __FILE__, __func__); + + if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { + const config_t *config = config_of_soc(); + tcss_configure(config->typec_aux_bias_pads); + } break; default: break; diff --git a/src/soc/intel/alderlake/include/soc/tcss.h b/src/soc/intel/alderlake/include/soc/tcss.h new file mode 100644 index 0000000..713528b --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/tcss.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_TCSS_H_ +#define _SOC_TCSS_H_ + +/* IOM aux bias control registers in REGBAR MMIO space */ +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 +#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088 +#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4) + +#endif /* _SOC_TCSS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Gerrit-Change-Number: 54089 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by chris wang (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 15: (2 comments) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/51523/comment/4c0560e6_326b46ec PS12, Line 27: > trailing whitespace Please fix. https://review.coreboot.org/c/coreboot/+/51523/comment/1c0a473f_19a2845a PS12, Line 32: > trailing whitespace Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 12:14:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by chris wang (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. chris wang has uploaded a new patch set (#15) to the change originally created by Kane Chen. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/shuboz/variant.c 4 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51523/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021