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Change in coreboot[master]: mb/ocp/deltalake: Configure IIO PCIe ports via FSP
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42096 ) Change subject: mb/ocp/deltalake: Configure IIO PCIe ports via FSP ...................................................................... mb/ocp/deltalake: Configure IIO PCIe ports via FSP Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/cpxsp_dl_iio.h M src/mainboard/ocp/deltalake/romstage.c M src/soc/intel/xeon_sp/cpx/acpi.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 5 files changed, 271 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42096/1 diff --git a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h index b7f8c85..b9535ff 100644 --- a/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h +++ b/src/mainboard/ocp/deltalake/cpxsp_dl_iio.h @@ -5,69 +5,82 @@ #include <FspmUpd.h> #include <soc/pci_devs.h> +#include <hob_iiouds.h> -#if 0 /* * DeltaLake Iio PCIe Port Table */ -static const UPD_PCI_PORT_CONFIG dl_iio_pci_port = { - // PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | - // DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | - // NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | - // NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | - // NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride -/* - { PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4A, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, - { PORT_4D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, - NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x00, 0x03 }, -*/ +static const UPD_IIO_PCIE_PORT_CONFIG dl_iio_pci_port[] = { + /* Socket | PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | + DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbIndex | + NtbPpd | NtbBarSizeOverride | NtbSplitBar | NtbBarSizeImBar1 | NtbBarSizeImBar2 + NtbBarSizeImBar2_0 | NtbBarSizeImBar2_1| NtbBarSizeEmBarSZ1 | NtbBarSizeEmBarSZ2 + NtbBarSizeEmBarSZ2_0 | NtbBarSizeEmBarSZ2_1 | NtbXlinkCtlOverride */ + /* PORT_1A ~ PORT_1D */ + { 0, PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_1D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_2A ~ PORT_2D */ + { 0, PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_2D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + /* PORT_3A ~ PORT_3D does not exist */ + /* PORT_4A ~ PORT_4D */ + { 0, PORT_4A, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4B, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4C, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, + { 0, PORT_4D, NOT_HIDE, 0x00, PcieAuto, 0x0, + 0xFF, 0xFF, 0xFF, 0x00, 0x1, 0xFF, + NTB_PORT_TRANSPARENT, 0x00, 0x00, 0x16, 0x16, + 0x0C, 0x0C, 0x16, 0x16, + 0x0C, 0x0C, 0x03}, }; -#endif /* * DeltaLake PCH PCIe Port Table diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index eabbd6b..ecfb910 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -61,13 +61,30 @@ uint8_t index; oem_update_iio(mupd); - -#if 0 - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *) dl_iio_pci_port; - mupd->FspmConfig.IioPciConfig.NumberOfEntries = - ARRAY_SIZE(dl_iio_pci_port); -#endif + /* Config IIO PCIe ports from table */ + mupd->FspmConfig.IioPcieConfigTablePtr = (uint32_t) dl_iio_pci_port; + mupd->FspmConfig.IioPcieConfigTableNumber = ARRAY_SIZE(dl_iio_pci_port); + /* Config all IIO PCIe ports? */ + mupd->FspmConfig.IIOPcieRootPortEnable = 1; + mupd->FspmConfig.DeEmphasis = 0x00; + mupd->FspmConfig.IIOPciePortLinkSpeed = PcieAuto; //0 + mupd->FspmConfig.IIOPcieMaxPayload = 0x0; + mupd->FspmConfig.DfxDnTxPreset = 0xFF; + mupd->FspmConfig.DfxRxPreset = 0xFF; + mupd->FspmConfig.DfxUpTxPreset = 0xFF; + mupd->FspmConfig.PcieCommonClock = 0x1; + mupd->FspmConfig.NtbPpd = NTB_PORT_TRANSPARENT; //0 + mupd->FspmConfig.NtbBarSizeOverride = 0x00; + mupd->FspmConfig.NtbSplitBar = 0x00; + mupd->FspmConfig.NtbBarSizeImBar1 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2 = 0x16; + mupd->FspmConfig.NtbBarSizeImBar2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeImBar2_1 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ1 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2 = 0x16; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_0 = 0x0C; + mupd->FspmConfig.NtbBarSizeEmBarSZ2_1 = 0x0C; + mupd->FspmConfig.NtbXlinkCtlOverride = 0x03; for (index = 0; index < ARRAY_SIZE(dl_pch_pci_port); index++) { mupd->FspmConfig.PchPcieForceEnable[dl_pch_pci_port[index].PortIndex] = diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 8cdd01e..6789e92 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -424,11 +424,11 @@ else if (p >= PORT_2A && p <= PORT_2D) return PSTACK1; else if (p >= PORT_4A && p <= PORT_4D) - return PSTACK2; + return PSTACK3; else if (p >= PORT_5A && p <= PORT_5D) - return PSTACK3; // MCP0 + return PSTACK4; // MCP0 else - return PSTACK4; // MCP1 + return MAX_STACKS; // MCP1 } static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 4374058..72a3b13 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -77,6 +77,9 @@ KTI_LINK5 } KTI_LOGIC_LINK; +#define HIDE 1 +#define NOT_HIDE 0 + #define IIO_BIFURCATE_xxxxxxxx 0xFE #define IIO_BIFURCATE_x4x4x4x4 0x0 #define IIO_BIFURCATE_x4x4xxx8 0x1 @@ -133,6 +136,44 @@ Iio_IouMax } IIO_IOUS; +typedef struct { + //For IioPcieConfig + UINT8 Socket; + UINT16 PortIndex; + UINT8 HidePort; + UINT8 DeEmphasis; + UINT8 PortLinkSpeed; + UINT8 MaxPayload; + UINT8 DfxDnTxPreset; + UINT8 DfxRxPreset; + UINT8 DfxUpTxPreset; + UINT8 Sris; + UINT8 PcieCommonClock; + //For IIO Ntb^M + UINT8 NtbIndex; + UINT8 NtbPpd; + UINT8 NtbBarSizeOverride; + UINT8 NtbSplitBar; + UINT8 NtbBarSizeImBar1; + UINT8 NtbBarSizeImBar2; + UINT8 NtbBarSizeImBar2_0; + UINT8 NtbBarSizeImBar2_1; + UINT8 NtbBarSizeEmBarSZ1; + UINT8 NtbBarSizeEmBarSZ2; + UINT8 NtbBarSizeEmBarSZ2_0; + UINT8 NtbBarSizeEmBarSZ2_1; + UINT8 NtbXlinkCtlOverride; +} UPD_IIO_PCIE_PORT_CONFIG; + +/** + NTB Per Port Definition + **/ +typedef enum { + NTB_PORT_TRANSPARENT = 0, + NTB_PORT_NTB_NTB +} NTB_PPD; + + /** UPD_PCH_PCIE_PORT: PortIndex - PCH PCIe Port Index. @@ -535,45 +576,160 @@ **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00F7 - PchAdrEn +/** Offset 0x00F7 +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00F8 - Usage type for IIO PCIE Config Table Ptr + IIO PCIE Config Table Ptr +**/ + UINT32 IioPcieConfigTablePtr; + +/** Offset 0x00FC - Usage type for IIO PCIE Config Table Number + IIO PCIE Config Table Number +**/ + UINT32 IioPcieConfigTableNumber; + +/** Offset 0x0100 - Usage type for IIO PCIE Root Port Enable or Disable + IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, + the value is 0x00 +**/ + UINT8 IIOPcieRootPortEnable; + +/** Offset 0x0101 - Usage type for IIO DeEmphasis + IIO DeEmphasis +**/ + UINT8 DeEmphasis; + +/** Offset 0x0102 - Usage type for IIO PCIE Root Port link speed + IIO root port link speed +**/ + UINT8 IIOPciePortLinkSpeed; + +/** Offset 0x0103 - Usage type for IIO PCIE Root Port Max Payload + IIO Root Port Max Payload +**/ + UINT8 IIOPcieMaxPayload; + +/** Offset 0x0104 - Usage type for IIO DfxDnTxPreset + IIO DfxDnTxPreset +**/ + UINT8 DfxDnTxPreset; + +/** Offset 0x0105 - Usage type for IIO DfxRxPreset + IIO DfxRxPreset +**/ + UINT8 DfxRxPreset; + +/** Offset 0x0106 - Usage type for IIO DfxUpTxPreset + IIO DfxUpTxPreset +**/ + UINT8 DfxUpTxPreset; + +/** Offset 0x0107 - Usage type for IIO PcieCommonClock + IIO PcieCommonClock +**/ + UINT8 PcieCommonClock; + +/** Offset 0x0108 - Usage type for IIO NtbPpd + IIO NtbPpd +**/ + UINT8 NtbPpd; + +/** Offset 0x0109 - Usage type for IIO NtbBarSizeOverride + IIO NtbBarSizeOverride +**/ + UINT8 NtbBarSizeOverride; + +/** Offset 0x010A - Usage type for IIO NtbSplitBar + IIO NtbSplitBar +**/ + UINT8 NtbSplitBar; + +/** Offset 0x010B - Usage type for IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1 +**/ + UINT8 NtbBarSizeImBar1; + +/** Offset 0x010C - Usage type for IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2 +**/ + UINT8 NtbBarSizeImBar2; + +/** Offset 0x010D - Usage type for IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0 +**/ + UINT8 NtbBarSizeImBar2_0; + +/** Offset 0x010E - Usage type for IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1 +**/ + UINT8 NtbBarSizeImBar2_1; + +/** Offset 0x010F - Usage type for IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1 +**/ + UINT8 NtbBarSizeEmBarSZ1; + +/** Offset 0x0110 - Usage type for IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2 +**/ + UINT8 NtbBarSizeEmBarSZ2; + +/** Offset 0x0111 - Usage type for IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0 +**/ + UINT8 NtbBarSizeEmBarSZ2_0; + +/** Offset 0x0112 - Usage type for IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1 +**/ + UINT8 NtbBarSizeEmBarSZ2_1; + +/** Offset 0x0113 - Usage type for IIO NtbXlinkCtlOverride + IIO NtbXlinkCtlOverride +**/ + UINT8 NtbXlinkCtlOverride; + +/** Offset 0x0114 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x00F8 - } TYPE:{Combo +/** Offset 0x0115 - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x00F9 - PCH PCIE PLL Ssc +/** Offset 0x0116 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x00FA - Usage type for PCH PCIE Root Port Index +/** Offset 0x0117 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x010E - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x012B - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0122 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x013F - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0136 +/** Offset 0x0153 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[1]; -/** Offset 0x0138 +/** Offset 0x0154 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -594,11 +750,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0148 +/** Offset 0x0164 **/ - UINT8 UnusedUpdSpace5[6]; + UINT8 UnusedUpdSpace6[2]; -/** Offset 0x014E +/** Offset 0x0166 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 7ac630f..79b7d7a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -102,6 +102,11 @@ PORT_2C, PORT_2D, // IOU2 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, + // IOU3 PORT_4A, PORT_4B, PORT_4C, -- To view, visit https://review.coreboot.org/c/coreboot/+/42096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cff6d71588f91c3210cbaa17484644d5b89cc62 Gerrit-Change-Number: 42096 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp2_0: Add weak function soc_fsp_get_version for SoC override
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47603 ) Change subject: intel/fsp2_0: Add weak function soc_fsp_get_version for SoC override ...................................................................... intel/fsp2_0: Add weak function soc_fsp_get_version for SoC override SoC can implement their own FSP version format and add to coreboot table LB_TAG_PLATFORM_BLOB_VERSION. Change-Id: I8d2427b7f7a2da9e8fe68e1494a2398b12802adc Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/util.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47603/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 315db05..7e6eede 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -97,7 +97,7 @@ const struct hob_header *fsp_next_hob(const struct hob_header *parent); bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]); void fsp_find_bootloader_tolum(struct range_entry *re); -void fsp_get_version(char *buf); +void soc_fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); void soc_validate_fsp_version(const struct fsp_header *hdr); diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 490816d..cf5583b 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -213,7 +213,7 @@ } /* Only call this function when FSP header has been read and validated */ -void fsp_get_version(char *buf) +__weak void soc_fsp_get_version(char *buf) { struct fsp_header *hdr = &fsps_hdr; union fsp_revision revision; @@ -231,7 +231,7 @@ size_t len; char fsp_version[FSP_VER_LEN] = {0}; - fsp_get_version(fsp_version); + soc_fsp_get_version(fsp_version); rec = (struct lb_string *)lb_new_record(header); rec->tag = LB_TAG_PLATFORM_BLOB_VERSION; len = strlen(fsp_version); -- To view, visit https://review.coreboot.org/c/coreboot/+/47603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2427b7f7a2da9e8fe68e1494a2398b12802adc Gerrit-Change-Number: 47603 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch
by Johnny Lin (Code Review) 12 May '21

12 May '21

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47560 ) Change subject: xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch ...................................................................... xeon_sp/cpx: Check FSP version for WW45 and die if version mismatch Change-Id: I19082ec210a270649e203779757fe39cb2e284f7 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/fsp.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 3 files changed, 62 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47560/1 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e..a0d9797 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode -romstage-y += romstage.c ddr.c +romstage-y += romstage.c ddr.c fsp.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/cpx/fsp.c b/src/soc/intel/xeon_sp/cpx/fsp.c new file mode 100644 index 0000000..0358143 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/fsp.c @@ -0,0 +1,54 @@ +#include <console/console.h> +#include <fsp/util.h> +#include <FspmUpd.h> + +void soc_validate_fsp_version(const struct fsp_header *hdr) +{ + bool mismatch = false; + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + revision.val = hdr->fsp_revision; + + if (((hdr->spec_version >> 4) != CPX_SPEC_MAJOR)) { + printk(BIOS_ALERT, "FSP spec major version %d doesn't match!\n", + hdr->spec_version >> 4); + mismatch = true; + } + if (((hdr->spec_version & 0xf) != CPX_SPEC_MINOR)) { + printk(BIOS_ALERT, "FSP spec minor version %d doesn't match!\n", + hdr->spec_version & 0xf); + mismatch = true; + } + if (revision.rev.major != CPX_REV_MAJOR) { + printk(BIOS_ALERT, "FSP revision major version %d doesn't match!\n", + revision.rev.major); + mismatch = true; + } + if (revision.rev.minor != CPX_REV_MINOR) { + printk(BIOS_ALERT, "FSP revision minor version %d doesn't match!\n", + revision.rev.minor); + mismatch = true; + } + if (revision.rev.revision != CPX_REV_VER) { + printk(BIOS_ALERT, "FSP revision version %d doesn't match!\n", + revision.rev.revision); + mismatch = true; + } + if (revision.rev.bld_num != CPX_REV_BUILD) { + printk(BIOS_ALERT, "FSP revision build number %d doesn't match!\n", + revision.rev.bld_num); + mismatch = true; + } + + if (mismatch) + die("FSP version is not correct\n"); + + printk(BIOS_INFO, "FSP version is expected\n"); +} diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index b4d4cad..15de4be 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -64,7 +64,13 @@ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE} #define CPXSP_2S6KTI_EPARAM_TABLE_COUNT 12 // NOTE - needs to match number of elements in CPXSP_2S6KTI_EPARAM_TABLE - +/* FSP version */ +#define CPX_SPEC_MAJOR 2 +#define CPX_SPEC_MINOR 1 +#define CPX_REV_MAJOR 0 +#define CPX_REV_MINOR 2 +#define CPX_REV_VER 1 +#define CPX_REV_BUILD 45 #pragma pack(1) -- To view, visit https://review.coreboot.org/c/coreboot/+/47560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19082ec210a270649e203779757fe39cb2e284f7 Gerrit-Change-Number: 47560 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52762 ) Change subject: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution ...................................................................... Patch Set 6: (1 comment) File src/cpu/amd/pi/00730F01/model_16_init.c: https://review.coreboot.org/c/coreboot/+/52762/comment/caa9e74e_46fd1788 PS4, Line 28: /* > Since apu2 is the only platform using this, there is no need for that, because apu2 does not support […] oh, ok -- To view, visit https://review.coreboot.org/c/coreboot/+/52762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2d7a75affd7d3d3a1bc6327fb423e206b28562f Gerrit-Change-Number: 52762 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 12 May 2021 14:44:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Report missing resources
by Felix Held (Code Review) 12 May '21

12 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52927 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Report missing resources ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Gerrit-Change-Number: 52927 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 12 May 2021 14:43:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek: Align code indent with code flow
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Attention is currently required from: Xi Chen. Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54096 ) Change subject: vc/mediatek: Align code indent with code flow ...................................................................... vc/mediatek: Align code indent with code flow gcc 11 suspects missing braces here, but it seems the line should be executed in all cases, so unindent it. Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/54096/1 diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c index cd897ed..ffdf3d6 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c @@ -3097,8 +3097,8 @@ else u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0; - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) - | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); } vSetRank(p, u1Rank_bak); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108 Gerrit-Change-Number: 54096 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: src/security/tpm: Deal with zero length tlcl writes
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Attention is currently required from: Christian Walter. Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54095 ) Change subject: src/security/tpm: Deal with zero length tlcl writes ...................................................................... src/security/tpm: Deal with zero length tlcl writes While memcpy(foo, bar, 0) should be a no-op, that's hard to prove for a compiler and so gcc 11.1 complains about the use of an uninitialized "bar" even though it's harmless in this case. Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/security/tpm/tss/tcg-1.2/tss.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/54095/1 diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 8b7778d..413b681 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -215,7 +215,8 @@ to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_write_cmd.length, length); - memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); + if (length > 0) + memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); return tlcl_send_receive(cmd.buffer, response, sizeof(response)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 Gerrit-Change-Number: 54095 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: src: Match array format in function declarations and definitions
by Patrick Georgi (Code Review) 12 May '21

12 May '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54094 ) Change subject: src: Match array format in function declarations and definitions ...................................................................... src: Match array format in function declarations and definitions gcc 11.1 complains when we're passing a type* into a function that was declared to get a type[], even if the ABI has identical parameter passing for both. To prepare for newer compilers, adapt to this added constraint. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/soc/intel/alderlake/espi.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c M src/vendorcode/mediatek/mt8192/dramc/dramc_top.c 12 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/54094/1 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index b4766ed..aa3462a 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -15,7 +15,7 @@ sysinfo->enable_peg = peg; } -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x51; diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 46cedfb..6764644 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -3,7 +3,7 @@ #include <southbridge/intel/common/gpio.h> #include <northbridge/intel/gm45/gm45.h> -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x51; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index be8ba5d..dabef34 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -2,7 +2,7 @@ #include <northbridge/intel/gm45/gm45.h> -void get_mb_spd_addrmap(u8 *spd_addrmap) +void get_mb_spd_addrmap(u8 spd_addrmap[4]) { spd_addrmap[0] = 0x50; spd_addrmap[2] = 0x52; diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index feec465..dd0edcd 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -20,7 +20,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 20704e5..0e63e0d 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -17,7 +17,7 @@ #include "chip.h" -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 1737a47..46646d8 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 489fe34..d634cf8 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index c3b50de..1d1f94e 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -16,7 +16,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 5abae76..5d38bb8 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -14,7 +14,7 @@ #include "chip.h" -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 8386cd9..4278676 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -22,7 +22,7 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index f0cb6db..dad0a49 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -8,7 +8,7 @@ #include <chip.h> -void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { const config_t *config = config_of_soc(); diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c index 8af6a36..04fd62a 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_top.c @@ -475,7 +475,7 @@ #if (FOR_DV_SIMULATION_USED==0) #if !__FLASH_TOOL_DA__ && !__ETT__ -void get_dram_rank_size(u64 dram_rank_size[DRAMC_MAX_RK]) +void get_dram_rank_size(u64 dram_rank_size[]) { #ifdef COMBO_MCP int index, rank_nr, i; -- To view, visit https://review.coreboot.org/c/coreboot/+/54094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Gerrit-Change-Number: 54094 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition
by Rob Barnes (Code Review) 12 May '21

12 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 ) Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/54070/comment/79d93ae1_fdfdc5ae PS2, Line 522: espi_write32(ESPI_SLAVE0_INT_STS, Can this just be espi_clear_status() or espi_write(ESPI_SLAVE0_INT_STS, status)? -- To view, visit https://review.coreboot.org/c/coreboot/+/54070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a Gerrit-Change-Number: 54070 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 May 2021 14:40:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/txt: Split of microcode error type printing
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54092 ) Change subject: security/intel/txt: Split of microcode error type printing ...................................................................... Patch Set 3: (1 comment) File src/security/intel/txt/logging.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119161): https://review.coreboot.org/c/coreboot/+/54092/comment/9b480fa4_39a91b40 PS3, Line 58: printk(BIOS_ERR, "%s\n", intel_txt_microcode_error_type(txt_error & TXT_ERROR_MASK)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/54092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I435de402fef6d4702c9c7250c8bd31243a04a46e Gerrit-Change-Number: 54092 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 12 May 2021 14:40:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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