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Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/54070/comment/2ae5d564_57b4de73
PS2, Line 522: espi_write32(ESPI_SLAVE0_INT_STS,
> Can this just be espi_clear_status() or espi_write(ESPI_SLAVE0_INT_STS, status)?
Done
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Hello Jason Glenesk, build bot (Jenkins), Furquan Shaikh, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition
......................................................................
soc/amd/common/block/espi_util: Workaround in-band reset race condition
When performing an in-band reset the host controller and the
peripheral can have mismatched IO configs.
i.e., The eSPI peripheral can be in IO-4 mode while, the
eSPI host will be in IO-1. This results in the peripheral
getting invalid packets and thus not responding.
If the peripheral is alerting when we perform an in-band
reset, there is a race condition in espi_send_command.
1) espi_send_command clears the interrupt status.
2) eSPI host controller hardware notices the alert and sends
a GET_STATUS.
3) espi_send_command writes the in-band reset command.
4) eSPI hardware enqueues the in-band reset until GET_STATUS
is complete.
5) GET_STATUS fails with NO_RESPONSE and sets the interrupt
status.
6) eSPI hardware performs in-band reset.
7) espi_send_command checks the status and sees a
NO_RESPONSE bit.
As a workaround we allow the NO_RESPONSE status code when
we perform an in-band reset.
BUG=b:186135022
TEST=suspend_stress_test and S5->S0 tests on guybrush. Verified S3
suspend and S5 resume on zork.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I71271377f20eaf29032214be98794e1645d9b70a
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/54070/3
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54073 )
Change subject: soc/amd/cezanne/chip.h: add DPTC and tablet mode options
......................................................................
Patch Set 1: Code-Review+2
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52908 )
Change subject: mb/google/guybrush: Configure wake resource for WiFi
......................................................................
mb/google/guybrush: Configure wake resource for WiFi
In order to support wake on WLAN events, configure the wake resource.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource
is added to SSDT.
Device (\_SB.PCI0.GP20.WF00)
{
Name (_UID, 0x38B82CBC) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.GP20.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x08,
0x03
})
}
Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
2 files changed, 7 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 8c23cf0..9a69dd0 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -16,6 +16,7 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_UART_ACPI
+ select DRIVERS_WIFI_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 1d01fff..a5ec351 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -53,7 +53,12 @@
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device domain 0 on
- device ref gpp_bridge_0 on end # WLAN
+ device ref gpp_bridge_0 on
+ chip drivers/wifi/generic
+ register "wake" = "GEVENT_8"
+ device pci 00.0 on end
+ end
+ end # WLAN
device ref gpp_bridge_1 on end # SD
device ref gpp_bridge_2 on end # WWAN
device ref gpp_bridge_3 on end # NVMe
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Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54072 )
Change subject: tests: code coverage improvements
......................................................................
Patch Set 2:
(3 comments)
File tests/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/54072/comment/83409d1d_fb6716b2
PS1, Line 180: ifeq ($(COV),1)
> So there are two options, the one I outlined below, or setting COV=1 if MAKECMDGOALS contains covera […]
I decided to use Patrick's suggestion; if you make coverage-report-tests or clean-coverage-report-tests without COV=1, then the makefile will set COV=1 and call $(MAKE) for that target.
https://review.coreboot.org/c/coreboot/+/54072/comment/9ff8893f_7e7a512e
PS1, Line 181: coverage-report-tests:
> Not a huge fan of using make targets for all kinds of batch processing, but given how we do that for […]
Done
https://review.coreboot.org/c/coreboot/+/54072/comment/a290cc37_cedc2c88
PS1, Line 187: @echo Please use COV=1 when creating code coverage reports.
> simplest solution could be calling `$(MAKE) coverage-report-tests COV=1` here, no?
Done
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Hello build bot (Jenkins), Jakub Czapiga, Julius Werner,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: tests: code coverage improvements
......................................................................
tests: code coverage improvements
Fix the exclusion path for lcov; it should exclude the directory
with source code, not object files.
Use the COV environment variable to
* control whether we build for coverage or not
* select the output directory
Add a separate target for generating the report, so we can get a
report for all of the tests together or just a single test.
Add documentation.
Signed-off-by: Paul Fagerburg <pfagerburg(a)google.com>
Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a
---
A Documentation/technotes/2021-05-code-coverage.md
M Documentation/tutorial/part3.md
M tests/Makefile.inc
3 files changed, 114 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/54072/2
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53905 )
Change subject: psp_verstage: remove not-implemented files for cezanne
......................................................................
psp_verstage: remove not-implemented files for cezanne
Cezanne PSP is missing implementations for some svc apis. Do not
include files related to missing svc apis.
This CL should be reverted after the cezanne PSP supports these
functions.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53905
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin Roth <martinroth(a)google.com>
---
M src/soc/amd/common/psp_verstage/Makefile.inc
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/common/psp_verstage/Makefile.inc b/src/soc/amd/common/psp_verstage/Makefile.inc
index a913a5b..7272de4 100644
--- a/src/soc/amd/common/psp_verstage/Makefile.inc
+++ b/src/soc/amd/common/psp_verstage/Makefile.inc
@@ -14,9 +14,12 @@
verstage-y += printk.c
verstage-y += psp_verstage.c
verstage-y += psp.c
+ifneq ($(CONFIG_SOC_AMD_CEZANNE),y)
+# cezanne PSP does not support these functions yet (b/187906425)
verstage-y += reset.c
verstage-y += timer.c
verstage-y += vboot_crypto.c
+endif
$(obj)/psp_verstage.bin: $(objcbfs)/verstage.elf
$(OBJCOPY_verstage) -O binary $^ $@
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Change subject: psp_verstage: remove not-implemented files for cezanne
......................................................................
Patch Set 3: Code-Review+2
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