coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/alderlake: Add known GPIO virtual wire information
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54088 ) Change subject: soc/intel/alderlake: Add known GPIO virtual wire information ...................................................................... soc/intel/alderlake: Add known GPIO virtual wire information GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. This patch is ported form tigerlake. Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> --- M src/soc/intel/alderlake/gpio.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/54088/1 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 25f8a3c..6d9e184 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -5,6 +5,8 @@ #include <soc/pcr_ids.h> #include <soc/pmc.h> +#define DEFAULT_VW_BASE 0x10 + /* * This file is created based on Intel Alder Lake Processor PCH Datasheet * Document number: 630094 @@ -39,12 +41,22 @@ INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64), /* GPP_A */ }; +static const struct vw_entries adl_community0_vw[] = { + {GPP_A0, GPP_A23}, + {GPP_B0, GPP_B23}, +}; + static const struct pad_group adl_community1_groups[] = { INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ }; +static const struct vw_entries adl_community1_vw[] = { + {GPP_D0, GPP_D19}, + {GPP_H0, GPP_H23}, +}; + /* This community is not visible to the OS */ static const struct pad_group adl_community2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ @@ -61,6 +73,12 @@ INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320), /* GPP_E */ }; +static const struct vw_entries adl_community4_vw[] = { + {GPP_F0, GPP_F23}, + {GPP_C0, GPP_C23}, + {GPP_E0, GPP_E23}, +}; + static const struct pad_group adl_community5_groups[] = { INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352), /* GPP_R */ INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK), /* GPP_SPI0 */ @@ -86,6 +104,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community0_groups, .num_groups = ARRAY_SIZE(adl_community0_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community0_vw, + .num_vw_entries = ARRAY_SIZE(adl_community0_vw), }, [COMM_1] = { /* GPP S, D, H */ .port = PID_GPIOCOM1, @@ -106,6 +127,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community1_groups, .num_groups = ARRAY_SIZE(adl_community1_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community1_vw, + .num_vw_entries = ARRAY_SIZE(adl_community1_vw), }, [COMM_2] = { /* GPD */ .port = PID_GPIOCOM2, @@ -165,6 +189,9 @@ .num_reset_vals = ARRAY_SIZE(rst_map), .groups = adl_community4_groups, .num_groups = ARRAY_SIZE(adl_community4_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community4_vw, + .num_vw_entries = ARRAY_SIZE(adl_community4_vw), }, [COMM_5] = { /* GPP R, SPI0 */ .port = PID_GPIOCOM5, -- To view, visit https://review.coreboot.org/c/coreboot/+/54088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Gerrit-Change-Number: 54088 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54087 ) Change subject: soc/intel/alderlake: Add known CPU Port IDs for GPIO communities ...................................................................... soc/intel/alderlake: Add known CPU Port IDs for GPIO communities Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/pcr_ids.h 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/54087/1 diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index ef6f6e4..25f8a3c 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -69,6 +69,7 @@ static const struct pad_community adl_communities[] = { [COMM_0] = { /* GPP B, T, A */ .port = PID_GPIOCOM0, + .cpu_port = PID_CPU_GPIOCOM0, .first_pad = GPIO_COM0_START, .last_pad = GPIO_COM0_END, .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, @@ -88,6 +89,7 @@ }, [COMM_1] = { /* GPP S, D, H */ .port = PID_GPIOCOM1, + .cpu_port = PID_CPU_GPIOCOM1, .first_pad = GPIO_COM1_START, .last_pad = GPIO_COM1_END, .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, @@ -126,6 +128,7 @@ }, [COMM_3] = { /* vGPIO */ .port = PID_GPIOCOM3, + .cpu_port = PID_CPU_GPIOCOM3, .first_pad = GPIO_COM3_START, .last_pad = GPIO_COM3_END, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, @@ -145,6 +148,7 @@ }, [COMM_4] = { /* GPP F, C, HVMOS, E */ .port = PID_GPIOCOM4, + .cpu_port = PID_CPU_GPIOCOM4, .first_pad = GPIO_COM4_START, .last_pad = GPIO_COM4_END, .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, @@ -164,6 +168,7 @@ }, [COMM_5] = { /* GPP R, SPI0 */ .port = PID_GPIOCOM5, + .cpu_port = PID_CPU_GPIOCOM5, .first_pad = GPIO_COM5_START, .last_pad = GPIO_COM5_END, .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index e4a29c4..9ea075a 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -33,6 +33,12 @@ #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb +/* CPU Port IDs */ +#define PID_CPU_GPIOCOM0 0xb7 +#define PID_CPU_GPIOCOM1 0xb8 +#define PID_CPU_GPIOCOM3 0xbb +#define PID_CPU_GPIOCOM4 0xb9 +#define PID_CPU_GPIOCOM5 0xba /* * SPI - DMI Destination ID -- To view, visit https://review.coreboot.org/c/coreboot/+/54087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Gerrit-Change-Number: 54087 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add IOM PCR PID
by Deepti Deshatty (Code Review) 12 May '21

12 May '21

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54086 ) Change subject: soc/intel/alderlake: Add IOM PCR PID ...................................................................... soc/intel/alderlake: Add IOM PCR PID Required for accessing IOM REGBAR space. Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> --- M src/soc/intel/alderlake/include/soc/pcr_ids.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/54086/1 diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index e05ecd8..e4a29c4 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -28,6 +28,7 @@ #define PID_PSF2 0xbb #define PID_PSF3 0xbc #define PID_PSF4 0xbd +#define PID_IOM 0xc1 #define PID_RTC 0xc3 #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb -- To view, visit https://review.coreboot.org/c/coreboot/+/54086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Gerrit-Change-Number: 54086 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kane Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Kangheui Won, Chris Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51523 to look at the new patch set (#14). Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/shuboz/variant.c 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51523/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 14 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kane Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Kangheui Won, Chris Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51523 to look at the new patch set (#13). Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz, as follow: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/shuboz/variant.c 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51523/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 13 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 12: (2 comments) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119143): https://review.coreboot.org/c/coreboot/+/51523/comment/cb2a54eb_781d06a6 PS12, Line 27: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119143): https://review.coreboot.org/c/coreboot/+/51523/comment/5029144c_7fc26d62 PS12, Line 32: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 12 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 May 2021 11:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kane Chen (Code Review) 12 May '21

12 May '21

Attention is currently required from: Kangheui Won, Kane Chen, Chris Wang. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Kangheui Won, Chris Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51523 to look at the new patch set (#12). Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... mb/google/zork/var/shuboz: update USB OC pin mapping modify USB OC pin setting for Shuboz, as follow: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 --- M src/mainboard/google/zork/variants/baseboard/helpers.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/shuboz/variant.c 4 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51523/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 12 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add display support for mipi panels
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52662 ) Change subject: sc7180: Add display support for mipi panels ...................................................................... Patch Set 6: (15 comments) File src/mainboard/google/trogdor/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/ad918524_a60c94a8 PS6, Line 104: if(CONFIG(TROGDOR_HAS_MIPI_PANEL)) space required before the open parenthesis '(' File src/soc/qualcomm/sc7180/display/dsi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/6300a538_4f04ab9f PS6, Line 65: write32(&dsi0->trig_ctrl,DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/ac27a67a_05369529 PS6, Line 172: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/f45286a4_141d5a41 PS6, Line 210: printk(BIOS_ERR, Invalid vsprintf pointer extension '%pk' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/1612ff8d_211f4027 PS6, Line 281: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/1eb25dec_254383fe PS6, Line 289: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/470aab37_b0a004c2 PS6, Line 292: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/5647fe08_fc76d41f PS6, Line 299: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/d8b97c3d_dec43f4c PS6, Line 302: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/e36d186b_a386e20a PS6, Line 319: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/db00ffb5_1d9cb6dc PS6, Line 322: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_DMA_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/c03b271d_dde8f664 PS6, Line 325: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_MDP_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/b3840075_690f3e60 PS6, Line 328: setbits32(&dsi0->int_ctrl,DSI_VIDEO_MODE_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/c3bba59b_5d65afb1 PS6, Line 333: setbits32(&dsi0->int_ctrl,DSI_ERROR_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119141): https://review.coreboot.org/c/coreboot/+/52662/comment/26ff5227_1508a1e3 PS6, Line 343: if(!pinfo && !pinfo->init_cmd) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... Patch Set 36: (1 comment) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119137): https://review.coreboot.org/c/coreboot/+/50586/comment/a8f59ead_766951c8 PS36, Line 499: while (1) suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 36 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:16:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by build bot (Jenkins) (Code Review) 12 May '21

12 May '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 ) Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... Patch Set 3: (5 comments) File payloads/libpayload/include/arm64/arch/io.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119135): https://review.coreboot.org/c/coreboot/+/53903/comment/5931baf4_8c8392fb PS3, Line 154: } void function return statements are not generally useful Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119135): https://review.coreboot.org/c/coreboot/+/53903/comment/40b429e7_194b113d PS3, Line 159: } void function return statements are not generally useful File src/commonlib/include/commonlib/coreboot_tables.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119135): https://review.coreboot.org/c/coreboot/+/53903/comment/4ea172a7_b2d1deb1 PS3, Line 332: uint32_t tag; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119135): https://review.coreboot.org/c/coreboot/+/53903/comment/fb54b93d_f95c8a26 PS3, Line 333: uint32_t size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119135): https://review.coreboot.org/c/coreboot/+/53903/comment/d4a8149b_55a9fd93 PS3, Line 334: void *config_base; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Wed, 12 May 2021 11:16:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021