coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
by Felix Held (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52584 to look at the new patch set (#4). Change subject: soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver ...................................................................... soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access it. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 --- M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/picasso/fsp_m_params.c M src/vendorcode/amd/fsp/cezanne/FspGuids.h M src/vendorcode/amd/fsp/picasso/FspGuids.h 5 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/52584/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Gerrit-Change-Number: 52584 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tests: Enable config override for tests
by Julius Werner (Code Review) 13 May '21

13 May '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... tests: Enable config override for tests Some tests require to change kconfig symbols values to cover the code. This patch enables one to set these vaues using <test-name>-config variable. Example for integer values. timestamp-test-config += CONFIG_HAVE_MONOTONIC_TIMER=1 Example for string values. Notice escaped quotes. spd_cache-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"SPD_CACHE_FMAP_NAME\" Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52937 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M tests/Makefile.inc 1 file changed, 18 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Paul Fagerburg: Looks good to me, approved diff --git a/tests/Makefile.inc b/tests/Makefile.inc index 44e3c69..cd25e0f 100644 --- a/tests/Makefile.inc +++ b/tests/Makefile.inc @@ -11,7 +11,7 @@ TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx TEST_DOTCONFIG = $(testobj)/.config -TEST_KCONFIG_AUTOHEADER := $(testobj)/config.h +TEST_KCONFIG_AUTOHEADER := $(testobj)/config.src.h TEST_KCONFIG_AUTOCONFIG := $(testobj)/auto.conf TEST_KCONFIG_DEPENDENCIES := $(testobj)/auto.conf.cmd TEST_KCONFIG_SPLITCONFIG := $(testobj)/config @@ -52,7 +52,7 @@ TEST_LDFLAGS += -no-pie # Extra attributes for unit tests, declared per test -attributes:= srcs cflags mocks stage +attributes:= srcs cflags config mocks stage stages:= decompressor bootblock romstage smm verstage stages+= ramstage rmodule postcar libagesa @@ -83,9 +83,23 @@ # Create actual targets for unit test binaries # $1 - test name define TEST_CC_template -$($(1)-objs): TEST_CFLAGS+= \ + +# Generate custom config.h redefining given symbols +$(1)-config-file := $(obj)/$(1)/config.h +$$($(1)-config-file): $(TEST_KCONFIG_AUTOHEADER) + mkdir -p $$(dir $$@) + printf '// File generated by tests/Makefile.inc\n// Do not change\n' > $$@ + printf '#include <%s>\n\n' "$(notdir $(TEST_KCONFIG_AUTOHEADER))" >> $$@ + for kv in $$($(1)-config); do \ + key="`echo $$$$kv | cut -d '=' -f -1`"; \ + value="`echo $$$$kv | cut -d '=' -f 2-`"; \ + printf '#undef %s\n' "$$$$key" >> $$@; \ + printf '#define %s %s\n\n' "$$$$key" "$$$$value" >> $$@; \ + done + +$($(1)-objs): TEST_CFLAGS += -I$$(dir $$($(1)-config-file)) \ -D__$$(shell echo $$($(1)-stage) | tr '[:lower:]' '[:upper:]')__ -$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $(TEST_KCONFIG_AUTOHEADER) +$($(1)-objs): $(obj)/$(1)/%.o: $$$$*.c $$($(1)-config-file) mkdir -p $$(dir $$@) $(HOSTCC) $(HOSTCFLAGS) $$(TEST_CFLAGS) $($(1)-cflags) -MMD \ -MT $$@ -c $$< -o $$@ -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: tests: Enable config override for tests
by Julius Werner (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52937 ) Change subject: tests: Enable config override for tests ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aeb78362c2609fbefbfd91c0f58ec19ed258ee1 Gerrit-Change-Number: 52937 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 13 May 2021 00:15:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cbfs: Increase mcache size defaults
by Julius Werner (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin. Hello Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54146 to review the following change. Change subject: cbfs: Increase mcache size defaults ...................................................................... cbfs: Increase mcache size defaults The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 --- M src/arch/x86/Kconfig M src/lib/Kconfig M src/mainboard/google/volteer/Kconfig M src/security/vboot/Kconfig 4 files changed, 14 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/54146/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index bb03db2..a488b55 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -147,9 +147,10 @@ config CBFS_MCACHE_SIZE hex depends on !NO_CBFS_MCACHE - default 0x2000 + default 0x4000 help - Increase this value if you see CBFS mcache overflow warnings. + Increase this value if you see CBFS mcache overflow warnings. Do NOT + change this value for vboot RW updates! config PC80_SYSTEM bool diff --git a/src/lib/Kconfig b/src/lib/Kconfig index e1d56fe..239f613 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -98,14 +98,3 @@ the associated CAR/SRAM size. In that case every single CBFS file lookup must re-read the same CBFS directory entries from flash to find the respective file. - -config CBFS_MCACHE_RW_PERCENTAGE - int - depends on VBOOT && !NO_CBFS_MCACHE - default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only - default 50 - help - The amount of the CBFS_MCACHE area that's used for the RW CBFS, in - percent from 0 to 100. The remaining area will be used for the RO - CBFS. Default is an even 50/50 split. When VBOOT is disabled, this - will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 2fec5be..3112672 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -161,12 +161,4 @@ bool default n -config CBFS_MCACHE_RW_PERCENTAGE - int - default 50 - -config CBFS_MCACHE_SIZE - hex - default 0x4000 - endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a39680d..515efc7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -235,6 +235,17 @@ Add a space-delimited list of filenames that should only be in the RW-B section. +config CBFS_MCACHE_RW_PERCENTAGE + int "Percentage of CBFS metadata cache used for RW CBFS" + depends on !NO_CBFS_MCACHE + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). + Do NOT change this value for vboot RW updates! + config VBOOT_ENABLE_CBFS_FALLBACK bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/54146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Gerrit-Change-Number: 54146 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/chip.h: add DPTC and tablet mode options
by Felix Held (Code Review) 13 May '21

13 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54073 ) Change subject: soc/amd/cezanne/chip.h: add DPTC and tablet mode options ...................................................................... soc/amd/cezanne/chip.h: add DPTC and tablet mode options Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/54073 Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/chip.h 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Raul Rangel: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 244f2ba..e770670 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -75,6 +75,14 @@ uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; + /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ + uint8_t dptc_enable; + + /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; + uint32_t thermctl_limit_tablet_mode_degreeC; }; #endif /* CEZANNE_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa Gerrit-Change-Number: 54073 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kangheui Won (Code Review) 13 May '21

13 May '21

Attention is currently required from: Kane Chen, Chris Wang, chris wang. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Wed, 12 May 2021 23:14:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... mb/google/guybrush: Add SoC thermal zone The time constant values were taken from the zork thermal.asl. BUG=b:186166365 TEST=Boot guybrush to OS and verify logs look correct thermal-0294 thermal_trips_update : Found critical threshold [3641] thermal-0321 thermal_trips_update : No hot threshold thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS thermal-0200 thermal_get_temperatur: Temperature is 3060 dK thermal LNXTHERM:00: registered as thermal_zone0 ACPI: Thermal Zone [TM00] (33 C) thermal-0200 thermal_get_temperatur: Temperature is 3070 dK Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54134/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 8c23cf0..9dba79c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -11,6 +11,7 @@ select BOARD_ROMSIZE_KB_16384 select DISABLE_KEYBOARD_RESET_PIN select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_ACPI_THERMAL_ZONE select DRIVERS_AMD_I2S_MACHINE_DEV select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 1d01fff..1a019b4 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,6 +52,30 @@ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + chip drivers/acpi/thermal_zone + register "name" = ""SOC"" + + register "temperature_sensor_id" = "0" + + register "polling_period" = "10000" + + # EC is configured to power off the system at 92C, so add one degree of buffer + # so the OS can gracefully shutdown + register "critical_temperature" = "91" + + # EC is configured to assert PROCHOT at 90C. That drastically lowers + # performance. Instead we will tell the OS to start throttling the CPUs at + # 85C in hopes that we don't hit the PROCHOT limit. + register "passive_config" = "{ + .temperature = 85, + .time_constant_1 = 2, + .time_constant_2 = 5, + .time_sampling_period = 2000, + }" + + device generic 0 on end + end + device domain 0 on device ref gpp_bridge_0 on end # WLAN device ref gpp_bridge_1 on end # SD -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE
by Raul Rangel (Code Review) 13 May '21

13 May '21

Attention is currently required from: Tim Wawrzynczak. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54133 ) Change subject: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE ...................................................................... ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE This generates the required method to access temperature data from the ChromeEC. BUG=b:186166365 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/thermal_zone.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54133/1 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index a37d673..a647b09 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -43,6 +43,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SWITCHES) += switches.c ramstage-$(CONFIG_DRIVERS_INTEL_DPTF) += ec_dptf_helpers.c +ramstage-$(CONFIG_DRIVERS_ACPI_THERMAL_ZONE) += thermal_zone.c CHROMEEC_SOURCE ?= $(top)/3rdparty/chromeec diff --git a/src/ec/google/chromeec/thermal_zone.c b/src/ec/google/chromeec/thermal_zone.c new file mode 100644 index 0000000..6031851 --- /dev/null +++ b/src/ec/google/chromeec/thermal_zone.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include "drivers/acpi/thermal_zone/chip.h" + +enum cb_err acpigen_write_thermal_zone_get_temperature( + const struct drivers_acpi_thermal_zone_config *config) +{ + acpigen_write_method_serialized("_TMP", 0); + + acpigen_emit_byte(RETURN_OP); + /* TODO: Can we search for the CrosEC device? */ + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.TSRD"); + acpigen_write_integer(config->temperature_sensor_id); + + acpigen_write_method_end(); + + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Gerrit-Change-Number: 54133 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... drivers/acpi: Add device tree driver to generate thermal zone Given the following device tree entry: chip drivers/acpi/thermal_zone register "name" = ""SOC"" register "temperature_sensor_id" = "0" register "polling_period" = "10000" # EC is configured to power off the system at 92C, so add one degree of buffer # so the OS can gracefully shutdown register "critical_temperature" = "91" # EC is configured to assert PROCHOT at 90C. That drastically lowers # performance. Instead we will tell the OS to start throttling the CPUs at # 85C in hopes that we don't hit the PROCHOT limit. register "passive_config" = "{ .temperature = 85, .time_constant_1 = 2, .time_constant_2 = 5, .time_sampling_period = 2000, }" device generic 0 on end end It will generate the following: Scope (\_TZ) { ThermalZone (TM00) { Name (_STR, "CPU") // _STR: Description String Name (_RTV, Zero) // _RTV: Relative Temperature Values Name (_TZP, 0x64) // _TZP: Thermal Zone Polling Name (_CRT, 0x0E39) // _CRT: Critical Temperature Name (_PSV, 0x0DFD) // _PSV: Passive Temperature Name (_PSL, Package (0x10) // _PSL: Passive List { \_SB.CP00, \_SB.CP01, \_SB.CP02, \_SB.CP03, \_SB.CP04, \_SB.CP05, \_SB.CP06, \_SB.CP07, \_SB.CP08, \_SB.CP09, \_SB.CP10, \_SB.CP11, \_SB.CP12, \_SB.CP13, \_SB.CP14, \_SB.CP15 }) Name (_TC1, 0x02) // _TC1: Thermal Constant 1 Name (_TC2, 0x05) // _TC2: Thermal Constant 2 Name (_TSP, 0x14) // _TSP: Thermal Sampling Period Method (_TMP, 0, Serialized) // _TMP: Temperature { Return (\_SB.PCI0.LPCB.EC0.TSRD (Zero)) } } } BUG=b:186166365 TEST=Boot guybrush to OS and verify thermal zone works Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d --- A src/drivers/acpi/thermal_zone/Kconfig A src/drivers/acpi/thermal_zone/Makefile.inc A src/drivers/acpi/thermal_zone/chip.h A src/drivers/acpi/thermal_zone/thermal_zone.c 4 files changed, 168 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/54132/1 diff --git a/src/drivers/acpi/thermal_zone/Kconfig b/src/drivers/acpi/thermal_zone/Kconfig new file mode 100644 index 0000000..d47aac2 --- /dev/null +++ b/src/drivers/acpi/thermal_zone/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_ACPI_THERMAL_ZONE + bool + default n + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/acpi/thermal_zone/Makefile.inc b/src/drivers/acpi/thermal_zone/Makefile.inc new file mode 100644 index 0000000..0a15b91 --- /dev/null +++ b/src/drivers/acpi/thermal_zone/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_ACPI_THERMAL_ZONE) += thermal_zone.c diff --git a/src/drivers/acpi/thermal_zone/chip.h b/src/drivers/acpi/thermal_zone/chip.h new file mode 100644 index 0000000..6f98253 --- /dev/null +++ b/src/drivers/acpi/thermal_zone/chip.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_ACPI_THERMAL_ZONE_H__ +#define __DRIVERS_ACPI_THERMAL_ZONE_H__ + +#include <types.h> + +/* + * All temperature units are in Celsius. + * All time units are in milliseconds. + */ +struct drivers_acpi_thermal_zone_config { + /* Name of the thermal zone */ + const char *name; + + /* Used to identify the temperature sensor */ + unsigned int temperature_sensor_id; + + /* The polling period in milliseconds for this thermal zone. */ + unsigned int polling_period; + + /* The temperature (_CRT) at which the OS must shutdown the system. */ + unsigned int critical_temperature; + + /* The temperature (_HOT) at which the OS may choose to hibernate the system */ + unsigned int hibernate_temperature; + + struct acpi_thermal_zone_passive_config { + /* + * The temperature (_PSV) at which the OS must activate passive cooling (i.e., + * throttle the CPUs). + */ + unsigned int temperature; + + /** + * DeltaP[%] = _TC1 * ( Tn - Tn-1 ) + _TC2 * (Tn - Tt) + * Where: + * Tn = current temperature + * Tt = target temperature (_PSV) + */ + unsigned int time_constant_1; + unsigned int time_constant_2; + unsigned int time_sampling_period; + + } passive_config; +}; + +/* + * SoC/Mainboard specific method (_TMP) to query a temperature sensor. + */ +enum cb_err acpigen_write_thermal_zone_get_temperature( + const struct drivers_acpi_thermal_zone_config *config); + +#endif /* __DRIVERS_ACPI_THERMAL_ZONE_H__ */ diff --git a/src/drivers/acpi/thermal_zone/thermal_zone.c b/src/drivers/acpi/thermal_zone/thermal_zone.c new file mode 100644 index 0000000..147f2bf --- /dev/null +++ b/src/drivers/acpi/thermal_zone/thermal_zone.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <assert.h> +#include <console/console.h> +#include <device/device.h> +#include <stdlib.h> + +#include "chip.h" + +#define TZ_DEVICE_PATH "\\_TZ" + +#define CELSIUS_TO_DECI_KELVIN(temp_c) ((temp_c) * 10 + 2731) +#define MILLISECONDS_TO_DECI_SECONDS(ms) ((ms) / 100) + +static const char *thermal_zone_acpi_name(const struct device *dev) +{ + char *name; + + if (dev->path.type != DEVICE_PATH_GENERIC) + return NULL; + + name = malloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "TM%02X", dev->path.generic.id); + name[4] = '\0'; + + return name; +} + +static void thermal_zone_fill_ssdt(const struct device *dev) +{ + struct drivers_acpi_thermal_zone_config *config = config_of(dev); + const char *scope; + const char *name; + + + assert(dev->path.type == DEVICE_PATH_GENERIC); + + if (dev->bus->dev->path.type == DEVICE_PATH_ROOT) + scope = "\\_TZ"; + else + scope = acpi_device_scope(dev); + + name = acpi_device_name(dev); + + assert(name); + assert(scope); + + printk(BIOS_INFO, "%s.%s: %s at %s\n", scope, name, dev->chip_ops->name, dev_path(dev)); + + acpigen_write_scope(scope); + acpigen_write_thermal_zone(name); + + if (config->name) + acpigen_write_name_string("_STR", config->name); + + /* All units are in K */ + acpigen_write_name_integer("_RTV", 0); + + if (config->polling_period) + acpigen_write_name_integer( + "_TZP", MILLISECONDS_TO_DECI_SECONDS(config->polling_period)); + + if (config->critical_temperature) + acpigen_write_name_integer( + "_CRT", CELSIUS_TO_DECI_KELVIN(config->critical_temperature)); + + if (config->hibernate_temperature) + acpigen_write_name_integer( + "_HOT", CELSIUS_TO_DECI_KELVIN(config->hibernate_temperature)); + + if (config->passive_config.temperature) { + acpigen_write_name_integer( + "_PSV", CELSIUS_TO_DECI_KELVIN(config->passive_config.temperature)); + + acpigen_write_processor_package("_PSL", 0, dev_count_cpu()); + + acpigen_write_name_integer("_TC1", config->passive_config.time_constant_1); + + acpigen_write_name_integer("_TC2", config->passive_config.time_constant_2); + + acpigen_write_name_integer( + "_TSP", MILLISECONDS_TO_DECI_SECONDS( + config->passive_config.time_sampling_period)); + } + + if (acpigen_write_thermal_zone_get_temperature(config) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to write _TMP for %s.%s\n", scope, name); + + acpigen_write_thermal_zone_end(); + acpigen_write_scope_end(); +} + +static struct device_operations thermal_zone_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = thermal_zone_acpi_name, + .acpi_fill_ssdt = thermal_zone_fill_ssdt, +}; + +static void thermal_zone_enable_dev(struct device *dev) +{ + dev->ops = &thermal_zone_ops; +} + +struct chip_operations drivers_acpi_thermal_zone_ops = { + CHIP_NAME("ACPI Thermal Zone") + .enable_dev = thermal_zone_enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add acpigen_write_thermal_zone
by Raul Rangel (Code Review) 13 May '21

13 May '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54131 ) Change subject: acpi: Add acpigen_write_thermal_zone ...................................................................... acpi: Add acpigen_write_thermal_zone BUG=b:186166365 TEST=Compiles Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/54131/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 5c8c1b9..9818dc2 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -781,6 +781,13 @@ acpigen_emit_namestring(name); } +void acpigen_write_thermal_zone(const char *name) +{ + acpigen_emit_ext_op(THERMAL_ZONE_OP); + acpigen_write_len_f(); + acpigen_emit_namestring(name); +} + void acpigen_write_STA(uint8_t status) { /* diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 0e8d29a..2d0bb77 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -338,6 +338,11 @@ { acpigen_pop_len(); } +void acpigen_write_thermal_zone(const char *name); +inline void acpigen_write_thermal_zone_end(void) +{ + acpigen_pop_len(); +} void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries); void acpigen_write_PPC(u8 nr); void acpigen_write_PPC_NVS(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/54131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Gerrit-Change-Number: 54131 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021