coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/volteer: Configure TCSS OC pins
by Nick Vaccaro (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Zhuohao Lee. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54076 to look at the new patch set (#5). Change subject: mb/google/volteer: Configure TCSS OC pins ...................................................................... mb/google/volteer: Configure TCSS OC pins TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/54076/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payload/tianocore: Drop IA32 option when UEFIPAYLOAD select
by Lance Zhao (Code Review) 13 May '21

13 May '21

Attention is currently required from: Lijian Zhao. Hello Lijian Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/54189 to review the following change. Change subject: payload/tianocore: Drop IA32 option when UEFIPAYLOAD select ...................................................................... payload/tianocore: Drop IA32 option when UEFIPAYLOAD select Since upstream edk2 totally drop 32-bit support for UefiPayload, prevent people select that in Config. Test: Build and run qemu successful boot up into EFI shell with UEFIPAYLOAD option.wq Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M payloads/external/tianocore/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/54189/1 diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 87b6e15..a1e24bc 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -45,6 +45,7 @@ config TIANOCORE_TARGET_IA32 bool "IA32" + depends on TIANOCORE_COREBOOTPAYLOAD help By selecting this option, the target architecture will be built for only IA32. -- To view, visit https://review.coreboot.org/c/coreboot/+/54189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Gerrit-Change-Number: 54189 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Attention: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security/tpm: Deal with zero length tlcl writes
by Jacob Garber (Code Review) 13 May '21

13 May '21

Attention is currently required from: Christian Walter. Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54095 ) Change subject: src/security/tpm: Deal with zero length tlcl writes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbffa508c2cd68790efbc0b4ab97ae1b4d85ad51 Gerrit-Change-Number: 54095 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 13 May 2021 04:45:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Provide RefreshWm for users to configurate
by Marx Wang (Code Review) 13 May '21

13 May '21

Marx Wang has restored this change. ( https://review.coreboot.org/c/coreboot/+/54079 ) Change subject: soc/intel/cannonlake: Provide RefreshWm for users to configurate ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/54079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic364df8b446f291f410e09825075f5b5251621ff Gerrit-Change-Number: 54079 Gerrit-PatchSet: 5 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in coreboot[master]: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54133 ) Change subject: ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONE ...................................................................... Patch Set 1: (1 comment) File src/ec/google/chromeec/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54133/comment/fe68c58f_c31fb62e PS1, Line 12: /* TODO: Can we search for the CrosEC device? */ partially... this is so ugly right now 😭 there is no proper `EC0` device in the devicetree hierarchy... see my comments in the next patch -- To view, visit https://review.coreboot.org/c/coreboot/+/54133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Gerrit-Change-Number: 54133 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 04:14:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Rob Barnes. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 ) Change subject: mb/google/guybrush: Add SoC thermal zone ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/54134/comment/d0a0d625_c7d9ebb3 PS1, Line 55: chip drivers/acpi/thermal_zone : register "name" = ""SOC"" : : register "temperature_sensor_id" = "0" : : register "polling_period" = "10000" : : # EC is configured to power off the system at 92C, so add one degree of buffer : # so the OS can gracefully shutdown : register "critical_temperature" = "91" : : # EC is configured to assert PROCHOT at 90C. That drastically lowers : # performance. Instead we will tell the OS to start throttling the CPUs at : # 85C in hopes that we don't hit the PROCHOT limit. : register "passive_config" = "{ : .temperature = 85, : .time_constant_1 = 2, : .time_constant_2 = 5, : .time_sampling_period = 2000, : }" : : device generic 0 on end : end If you add this chip/device underneath the EC, you might find it simpler to implement the chromeec callback for get_temperature because you will get a reference to the EC's `struct device`, and you can use acpi_device_path() -- To view, visit https://review.coreboot.org/c/coreboot/+/54134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3 Gerrit-Change-Number: 54134 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 04:13:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/acpi: Add device tree driver to generate thermal zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54132 ) Change subject: drivers/acpi: Add device tree driver to generate thermal zone ...................................................................... Patch Set 1: (7 comments) File src/drivers/acpi/thermal_zone/chip.h: https://review.coreboot.org/c/coreboot/+/54132/comment/4cd81c1f_494c6242 PS1, Line 13: /* Name of the thermal zone */ : const char *name; suggestion: since this is for _STR, maybe use `description` instead of `name` ? My first thought was that this was the ACPI name https://review.coreboot.org/c/coreboot/+/54132/comment/50da6b48_20135236 PS1, Line 20: polling_period suggestion: suffix with `_ms` https://review.coreboot.org/c/coreboot/+/54132/comment/30d1a4ba_f696c185 PS1, Line 28: acpi_thermal_zone_passive_config I don't think the struct name is required https://review.coreboot.org/c/coreboot/+/54132/comment/b4483278_bf3fa1dd PS1, Line 51: acpigen_write_thermal_zone_get_temperature that is one heck of a name there 😊 suggestion: `mainboard_acpigen_write_tz_get_temp` ? https://review.coreboot.org/c/coreboot/+/54132/comment/bfec19e7_49ccdff0 PS1, Line 52: drivers_acpi_thermal_zone_config I wonder if it's always necessary to pass this whole structure to this... File src/drivers/acpi/thermal_zone/thermal_zone.c: https://review.coreboot.org/c/coreboot/+/54132/comment/0585f761_be27322f PS1, Line 57: K deci-kelvin https://review.coreboot.org/c/coreboot/+/54132/comment/306d9abe_4bcd177c PS1, Line 87: if (acpigen_write_thermal_zone_get_temperature(config) != CB_SUCCESS) : printk(BIOS_ERR, "Failed to write _TMP for %s.%s\n", scope, name); Does this callback need to have a return value? If it's just to print an error, it seems like the callback could print something more specific anyway? -- To view, visit https://review.coreboot.org/c/coreboot/+/54132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Gerrit-Change-Number: 54132 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 04:10:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Karthik Ramasubramanian (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Dtrain Hsu, Henry Sun, Tim Wawrzynczak. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54057 ) Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... Patch Set 1: (4 comments) Patchset: PS1: @Furquan/Tim, Is it ok to enable fw_config in SMM stage? I am not sure if it was intentionally not enabled. File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54057/comment/a56594cb_2e666bdc PS1, Line 188: smm-$(CONFIG_FW_CONFIG) += fw_config.c Please move it to a separate change of its own. Definitely needs to be checked with wider audience based on the use-case. File src/mainboard/google/dedede/variants/cret/gpio.c: https://review.coreboot.org/c/coreboot/+/54057/comment/56b7d4d5_6d1d74bd PS1, Line 122: Instead of maintaining 2 large tables, can you please check if this approach works for you keeping the original table? static const struct pad_config lte_disable_pads = { PAD_NC(GPP_A10, NONE), PAD_NC(GPP_H17, NONE), }; static void fw_config_handle(void *unused) { if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); File src/mainboard/google/dedede/variants/cret/overridetree.cb: https://review.coreboot.org/c/coreboot/+/54057/comment/14a2e6dd_172eebf8 PS1, Line 88: probe LTE LTE_PRESENT Just want to remind that this works as long as you dont re-use the same USB port for a different use-case. -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 04:09:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6
by EricR Lai (Code Review) 13 May '21

13 May '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54173 ) Change subject: mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6 ...................................................................... mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6 PCIE6 only needed when use the PCIE LTE. BUG=b:180166408 BRANCH=none TEST=FM350 can/can't be detected when enable/disable this config. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/54173/1 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index e601f18..0c230af 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -43,6 +43,9 @@ device generic 0 on end end end + device ref pcie_rp6 on + probe DB_LTE LTE_PCIE + end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" -- To view, visit https://review.coreboot.org/c/coreboot/+/54173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Gerrit-Change-Number: 54173 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Add acpigen_write_thermal_zone
by Tim Wawrzynczak (Code Review) 13 May '21

13 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54131 ) Change subject: acpi: Add acpigen_write_thermal_zone ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Gerrit-Change-Number: 54131 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 03:50:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021