coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_...
by David Wu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Marco Chen. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52851 ) Change subject: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIG ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/dedede/variants/magolor/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52851/comment/e443b83e_6cc2cced PS5, Line 2: field CAMERA_WFC 38 40 > * Definition of SSFC bits in coreboot per variant or baseboard is all fine to me so nothing we need […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 01:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_...
by David Wu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Marco Chen. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52851 ) Change subject: mb/google/dedede/var/magolor: Select touchscreen based on SSFC in FW_CONFIG ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52851/comment/944a1dd1_3db551fc PS5, Line 7: Select touchscreen panel size based on SSFC value > Select touchscreen based on SSFC in FW_CONFIG Done https://review.coreboot.org/c/coreboot/+/52851/comment/dce6c544_0ed1e42c PS5, Line 9: Select tocuhscreen panel size for 11" and 14", based on : the value set in the SSFC_CONFIG. > Select touchscreen(s) based on touchscreen panel size provisioned in SSFC of CBI (higher 32 bits of […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3 Gerrit-Change-Number: 52851 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 01:46:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: change vpp_sel default mux for 4k support
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54082 ) Change subject: soc/mediatek/mt8195: change vpp_sel default mux for 4k support ...................................................................... soc/mediatek/mt8195: change vpp_sel default mux for 4k support vpp_sel and ethdr_sel are vdosys clock source select mux. Steps to change to support 4K source. 1. Change vpp_sel source to mainpll_d4 to run at 546MHz 2. Change ethdr_sel source to univpll_d6 to run at 416MHz Signed-off-by: Nancy Lin <nancy.lin(a)mediatek.com> Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54082 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/pll.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 6e85def..9e9718e 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -332,8 +332,8 @@ { .id = TOP_SCP_SEL, .sel = 7 }, /* 7: mainpll_d6_d2 */ { .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */ /* CLK_CFG_1 */ - { .id = TOP_VPP_SEL, .sel = 2 }, /* 2: mainpll_d5_d2 */ - { .id = TOP_ETHDR_SEL, .sel = 10 }, /* 10: mmpll_d5_d4 */ + { .id = TOP_VPP_SEL, .sel = 9 }, /* 9: mainpll_d4 */ + { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ { .id = TOP_CAM_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ /* CLK_CFG_2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6518ed6204528489c41e7161534bbd3734ac851 Gerrit-Change-Number: 54082 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: configure DMA buffer in DRAM
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54052 ) Change subject: soc/mediatek/mt8195: configure DMA buffer in DRAM ...................................................................... soc/mediatek/mt8195: configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/mmu_operations.c 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 67ceed3..a04ccf4 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c index 7018093..de6e8bc 100644 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -29,3 +29,10 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0 Gerrit-Change-Number: 54052 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: Enable SCP SRAM
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54014 ) Change subject: soc/mediatek/mt8195: Enable SCP SRAM ...................................................................... soc/mediatek/mt8195: Enable SCP SRAM Enable SCP SRAM to allow module in SCPSYS to access DRAM. TEST=AFE acess DRAM successfully Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54014 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/scp.h A src/soc/mediatek/mt8195/scp.c 4 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index cdb2681..ec7e4f9 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -6,6 +6,7 @@ #include <soc/mt6359p.h> #include <soc/pmif.h> #include <soc/rtc.h> +#include <soc/scp.h> void platform_romstage_main(void) { @@ -14,4 +15,5 @@ mt6315_init(); clk_buf_init(); rtc_boot(); + scp_rsi_enable(); } diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index efd4a12..67ceed3 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -27,6 +27,7 @@ romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8195/include/soc/scp.h b/src/soc/mediatek/mt8195/include/soc/scp.h new file mode 100644 index 0000000..c5c552b --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/scp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_SCP_H +#define SOC_MEDIATEK_MT8195_SCP_H + +#include <soc/addressmap.h> + +#define SCP_SRAM_PDN_DISABLE_VAL 0xFFFFFFFF + +#define REG_L1TCM_SRAM_PDN (void *)(SCP_CFG_BASE + 0x2102C) + +void scp_rsi_enable(void); +void scp_rsi_disable(void); +#endif diff --git a/src/soc/mediatek/mt8195/scp.c b/src/soc/mediatek/mt8195/scp.c new file mode 100644 index 0000000..3a3bc27 --- /dev/null +++ b/src/soc/mediatek/mt8195/scp.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/scp.h> + +void scp_rsi_enable(void) +{ + u32 val; + + for (val = SCP_SRAM_PDN_DISABLE_VAL; val != 0U;) { + val = val >> 1; + write32(REG_L1TCM_SRAM_PDN, val); + } +} + +void scp_rsi_disable(void) +{ + write32(REG_L1TCM_SRAM_PDN, SCP_SRAM_PDN_DISABLE_VAL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40862f8d74e5aa17361f1c91ea31a10b0a4ffb31 Gerrit-Change-Number: 54014 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kane Chen (Code Review) 13 May '21

13 May '21

Attention is currently required from: Chris Wang, chris wang. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 13 May 2021 01:16:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: factor out acpigen_write_alib_dptc to common code
by Felix Held (Code Review) 13 May '21

13 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54077 ) Change subject: soc/amd: factor out acpigen_write_alib_dptc to common code ...................................................................... soc/amd: factor out acpigen_write_alib_dptc to common code Also drop unneeded intermediate cast to void * before casting the address of the struct dptc_input type variables to uint8_t *. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 4 files changed, 33 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 3ed137c..f101680 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -195,29 +195,9 @@ config->sustained_power_limit_tablet_mode_mW, config->fast_ppt_limit_tablet_mode_mW, config->slow_ppt_limit_tablet_mode_mW); - /* Scope (\_SB) */ - acpigen_write_scope("\\_SB"); - /* Method(DPTC, 0, Serialized) */ - acpigen_write_method_serialized("DPTC", 0); - - /* TODO: The code assumes that if DPTC gets called the following object exists */ - /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); - - acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, - sizeof(tablet_mode_input)); - - /* Else */ - acpigen_write_else(); - - acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, - sizeof(default_input)); - - acpigen_pop_len(); /* Else */ - - acpigen_pop_len(); /* Method DPTC */ - acpigen_pop_len(); /* Scope \_SB */ + acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), + (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); } static void root_complex_fill_ssdt(const struct device *device) diff --git a/src/soc/amd/common/block/acpi/alib.c b/src/soc/amd/common/block/acpi/alib.c index 5e1e8fb..7dbb9b8 100644 --- a/src/soc/amd/common/block/acpi/alib.c +++ b/src/soc/amd/common/block/acpi/alib.c @@ -4,7 +4,7 @@ #include <amdblocks/alib.h> #include <types.h> -void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) +static void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) { /* Name (buf_name, Buffer(size) {...} */ acpigen_write_name(buf_name); @@ -15,3 +15,29 @@ acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); acpigen_emit_namestring(buf_name); } + +void acpigen_write_alib_dptc(uint8_t *default_param, size_t default_param_len, + uint8_t *tablet_param, size_t tablet_param_len) +{ + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Method(DPTC, 0, Serialized) */ + acpigen_write_method_serialized("DPTC", 0); + + /* TODO: The code assumes that if DPTC gets called the following object exists */ + /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); + + acpigen_dptc_call_alib("TABB", tablet_param, tablet_param_len); + + /* Else */ + acpigen_write_else(); + + acpigen_dptc_call_alib("DEFB", default_param, default_param_len); + + acpigen_pop_len(); /* Else */ + + acpigen_pop_len(); /* Method DPTC */ + acpigen_pop_len(); /* Scope \_SB */ +} diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index b9d34c5..61608d5 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,7 +21,8 @@ uint32_t value; } __packed; -void acpigen_dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size); +void acpigen_write_alib_dptc(uint8_t *default_param, size_t default_param_len, + uint8_t *tablet_param, size_t tablet_param_len); #endif /* !__ACPI__ */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 3517e3d..eee2036 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -193,28 +193,9 @@ config->sustained_power_limit_tablet_mode_mW, config->fast_ppt_limit_tablet_mode_mW, config->slow_ppt_limit_tablet_mode_mW); - /* Scope (\_SB) */ - acpigen_write_scope("\\_SB"); - /* Method(DPTC, 0, Serialized) */ - acpigen_write_method_serialized("DPTC", 0); - - /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ - acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); - - acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, - sizeof(tablet_mode_input)); - - /* Else */ - acpigen_write_else(); - - acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, - sizeof(default_input)); - - acpigen_pop_len(); /* Else */ - - acpigen_pop_len(); /* Method DPTC */ - acpigen_pop_len(); /* Scope \_SB */ + acpigen_write_alib_dptc((uint8_t *)&default_input, sizeof(default_input), + (uint8_t *)&tablet_mode_input, sizeof(tablet_mode_input)); } static void root_complex_fill_ssdt(const struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/54077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443 Gerrit-Change-Number: 54077 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/root_complex: generate DPTC ACPI method
by Felix Held (Code Review) 13 May '21

13 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54074 ) Change subject: soc/amd/cezanne/root_complex: generate DPTC ACPI method ...................................................................... soc/amd/cezanne/root_complex: generate DPTC ACPI method This adds support for convertible devices to support different maximum power and thermal configurations. The dynamic power and thermal configuration (DPTC) via ACPI ALIB calls allows to change the parameters during runtime. This code contains the assumption that \_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At the moment only chromeec declares EC0.TBMD, but it's also the only code that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to the common code directory, since it's currently unsure if we might need to configure more than those 4 parameters for Cezanne. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/root_complex.c 2 files changed, 76 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 327ec12..2cedf8c 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_ACP select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_ALIB select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 5d021ba..3ed137c 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> #include <amdblocks/acpi.h> +#include <amdblocks/alib.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -13,6 +15,37 @@ #include <fsp/util.h> #include <soc/iomap.h> #include <stdint.h> +#include "chip.h" + +#define DPTC_TOTAL_UPDATE_PARAMS 4 + +struct dptc_input { + uint16_t size; + struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; +} __packed; + +#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ + }, \ + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + }, \ + } /* * @@ -146,9 +179,51 @@ setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); } +static void acipgen_dptci(void) +{ + const struct soc_amd_cezanne_config *config = config_of_soc(); + + if (!config->dptc_enable) + return; + + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); + struct dptc_input tablet_mode_input = DPTC_INPUTS( + config->thermctl_limit_tablet_mode_degreeC, + config->sustained_power_limit_tablet_mode_mW, + config->fast_ppt_limit_tablet_mode_mW, + config->slow_ppt_limit_tablet_mode_mW); + /* Scope (\_SB) */ + acpigen_write_scope("\\_SB"); + + /* Method(DPTC, 0, Serialized) */ + acpigen_write_method_serialized("DPTC", 0); + + /* TODO: The code assumes that if DPTC gets called the following object exists */ + /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ + acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); + + acpigen_dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, + sizeof(tablet_mode_input)); + + /* Else */ + acpigen_write_else(); + + acpigen_dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, + sizeof(default_input)); + + acpigen_pop_len(); /* Else */ + + acpigen_pop_len(); /* Method DPTC */ + acpigen_pop_len(); /* Scope \_SB */ +} + static void root_complex_fill_ssdt(const struct device *device) { acpi_fill_root_complex_tom(device); + acipgen_dptci(); } static const char *gnb_acpi_name(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/54074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Gerrit-Change-Number: 54074 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [WIP] soc/amd/picasso/agesa_Acpi: add BERT support
by Felix Held (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54149 ) Change subject: [WIP] soc/amd/picasso/agesa_Acpi: add BERT support ...................................................................... [WIP] soc/amd/picasso/agesa_Acpi: add BERT support TODO: Find out why Linux complains about an invalid error record. This might be due to the way I force the code into the MCA error state in the NOTFORMERGE follow-up patch I use for testing or the layout of the generated data structure is wrong. TODO: investigate if we can just implement acpi_soc_fill_bert and acpi_is_boot_error_src_present instead of reimplementing the SSDT generation here. If it can be used, it should also be used on Stoneyridge where this is basically a copy from. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14577e80e722cb5ccf344a4520cf3adde669fc5e --- M src/soc/amd/picasso/agesa_acpi.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/54149/1 diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index abac9c1..806ee6a 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_crat.h> #include <acpi/acpi_ivrs.h> +#include <arch/bert_storage.h> #include <console/console.h> #include <cpu/amd/cpuid.h> #include <cpu/amd/msr.h> @@ -994,6 +995,7 @@ { acpi_ivrs_t *ivrs; struct acpi_crat_header *crat; + acpi_bert_t *bert; /* CRAT */ current = ALIGN(current, 8); @@ -1012,6 +1014,26 @@ current += ivrs->header.length; acpi_add_table(rsdp, ivrs); + /* BERT */ + if (CONFIG(ACPI_BERT) && bert_errors_present()) { + /* Skip the table if no errors are present. ACPI driver reports + * a table with a 0-length region: + * BERT: [Firmware Bug]: table invalid. + */ + void *rgn; + size_t size; + bert_errors_region(&rgn, &size); + if (!rgn) { + printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); + } else { + current = ALIGN(current, 8); + bert = (acpi_bert_t *)current; + acpi_write_bert(bert, (uintptr_t)rgn, size); + acpi_add_table(rsdp, (void *)current); + current += bert->header.length; + } + } + /* Add SRAT, MSCT, SLIT if needed in the future */ return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/54149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14577e80e722cb5ccf344a4520cf3adde669fc5e Gerrit-Change-Number: 54149 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] soc/amd/picasso/mca: use MCAX registers instead of legacy MCA
by Felix Held (Code Review) 13 May '21

13 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52616 to look at the new patch set (#3). Change subject: [WIP] soc/amd/picasso/mca: use MCAX registers instead of legacy MCA ...................................................................... [WIP] soc/amd/picasso/mca: use MCAX registers instead of legacy MCA Not verified yet. TODO: Still need to fully verify and possibly debug the code in build_bert_mca_error and the function it calls. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407 --- M src/soc/amd/picasso/mca.c 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/52616/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407 Gerrit-Change-Number: 52616 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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