coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/volteer/var/volteer2: Configure TCSS OC pins
by Nick Vaccaro (Code Review) 12 May '21

12 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Zhuohao Lee. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54076 ) Change subject: mb/google/volteer/var/volteer2: Configure TCSS OC pins ...................................................................... Patch Set 4: Code-Review-1 (1 comment) Patchset: PS4: I'm seeing issues that I think may be related to this patch. Setting to -1 until I verify. -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 21:24:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/genbuild_h: Update IASL location finding code
by Nico Huber (Code Review) 12 May '21

12 May '21

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54001 ) Change subject: util/genbuild_h: Update IASL location finding code ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54001/comment/7409843f_1357bfe7 PS2, Line 23: but on an initial build, this check couldn't find iasl. Is this hard to fix? As I understood CB:53997, we would only call genbuild_h on a regular build now. -- To view, visit https://review.coreboot.org/c/coreboot/+/54001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f8dca0be8bfb54d3c672fab6cf6f005bb394c3 Gerrit-Change-Number: 54001 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 12 May 2021 21:17:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable GFX HDA FSP UPD
by Raul Rangel (Code Review) 12 May '21

12 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54100 ) Change subject: soc/amd/cezanne: Enable GFX HDA FSP UPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Gerrit-Change-Number: 54100 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 May 2021 21:13:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Enable GFX HDA FSP UPD
by Karthik Ramasubramanian (Code Review) 12 May '21

12 May '21

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54100 ) Change subject: soc/amd/cezanne: Enable GFX HDA FSP UPD ...................................................................... soc/amd/cezanne: Enable GFX HDA FSP UPD By default, FSP disables the GFX HDA. Enable it to support HDMI Audio functionality. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Ensure that the GFX HDA is enumerated in lspci output. 04:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1637 Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/fsp_m_params.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/54100/1 diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 4aff7e0..5dd3056 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -8,10 +8,34 @@ #include <device/device.h> #include <fsp/api.h> #include <soc/platform_descriptors.h> +#include <soc/pci_devs.h> #include <string.h> #include <types.h> #include "chip.h" +static const struct device_path gfx_hda_path[] = { + { + .type = DEVICE_PATH_PCI, + .pci.devfn = PCIE_ABC_A_DEVFN + }, + { + .type = DEVICE_PATH_PCI, + .pci.devfn = GFX_HDA_DEVFN + }, +}; + +static bool devtree_gfx_hda_dev_enabled(void) +{ + const struct device *gfx_hda_dev; + + gfx_hda_dev = find_dev_nested_path(pci_root_bus(), gfx_hda_path, + ARRAY_SIZE(gfx_hda_path)); + if (!gfx_hda_dev) + return false; + + return gfx_hda_dev->enabled; +} + static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, const fsp_dxio_descriptor *descs, size_t num) { @@ -136,6 +160,8 @@ mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Gerrit-Change-Number: 54100 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/volteer2: Configure TCSS OC pins
by Tim Wawrzynczak (Code Review) 12 May '21

12 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54076 ) Change subject: mb/google/volteer/var/volteer2: Configure TCSS OC pins ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/54076/comment/68fcd07b_0ea26d27 PS3, Line 9: volteer > From what I've fopund, I think we're ok with setting this in baseboard. […] It does look like the vast majority of the variants used the same pad for OC3 ( I see lillipup doesn't set it either). I guess it's up to you, wouldn't hurt to double check with the EEs. -- To view, visit https://review.coreboot.org/c/coreboot/+/54076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Gerrit-Change-Number: 54076 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 12 May 2021 20:52:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/w541: Add Thinkpad W541
by amersel (Code Review) 12 May '21

12 May '21

Attention is currently required from: Peter Lemenkov, Alexander Couzens, Patrick Rudolph. amersel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52659 ) Change subject: mb/lenovo/w541: Add Thinkpad W541 ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52659/comment/1e5f50aa_8098dc18 PS9, Line 38: - Each boot takes 20s > Oh, sorry - I do not know what I was thinking of then I've asked you about this. […] Here's the boot log: https://pastebin.com/jC5vvCNn I'm booted into a dirty build, just to verify patch set 11 would compile and boot. There aren't other changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/52659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08 Gerrit-Change-Number: 52659 Gerrit-PatchSet: 11 Gerrit-Owner: amersel Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 12 May 2021 20:46:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Lemenkov <lemenkov(a)gmail.com> Comment-In-Reply-To: amersel Gerrit-MessageType: comment

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Change in coreboot[master]: vboot: Add VB2_CONTEXT_EC_IN_RO
by Daisuke Nojiri (Code Review) 12 May '21

12 May '21

Attention is currently required from: Daisuke Nojiri, Aaron Durbin. Hello build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54099 to look at the new patch set (#2). Change subject: vboot: Add VB2_CONTEXT_EC_IN_RO ...................................................................... vboot: Add VB2_CONTEXT_EC_IN_RO This patch makes coreboot set VB2_CONTEXT_EC_IN_RO based on the boot mode read from the GSC. Vboot will check VB2_CONTEXT_EC_IN_RO to determine whether the EC can be trusted or not. BUG=b:180927027, b:187871195 BRANCH=none TEST=build Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 --- M src/security/vboot/vboot_logic.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 Gerrit-Change-Number: 54099 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vboot: Add VB2_CONTEXT_EC_IN_RO
by Daisuke Nojiri (Code Review) 12 May '21

12 May '21

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54099 ) Change subject: vboot: Add VB2_CONTEXT_EC_IN_RO ...................................................................... vboot: Add VB2_CONTEXT_EC_IN_RO This patch makes coreboot set VB2_CONTEXT_EC_IN_RO based on the boot mode read from the GSC. Vboot will check VB2_CONTEXT_EC_IN_RO to determine whether the EC can be trusted or not. BUG=b:180927027, b:187871195 BRANCH= TEST= Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 --- M .gitignore M 3rdparty/amd_blobs M 3rdparty/arm-trusted-firmware M 3rdparty/blobs M 3rdparty/chromeec M 3rdparty/cmocka M 3rdparty/fsp M 3rdparty/intel-microcode M 3rdparty/libgfxinit M 3rdparty/libhwbase M 3rdparty/qc_blobs M 3rdparty/vboot M src/security/vboot/vboot_logic.c 13 files changed, 20 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/54099/1 diff --git a/.gitignore b/.gitignore index 11a6173..c003ba9 100644 --- a/.gitignore +++ b/.gitignore @@ -42,3 +42,4 @@ *.kdev4 doxygen/* +/3rdparty/ diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index dded82f..7874c7d 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit dded82f1435b8b8eb687faf38a05a9b1f31e9fa0 +Subproject commit 7874c7d3cebc0ebca57875e24911ddd55aec9711 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 7ad3981..ace2368 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 7ad39818b184850d263008e7d36ba16adf72a669 +Subproject commit ace23683beb81354d6edbc61c087ab8c384d0631 diff --git a/3rdparty/blobs b/3rdparty/blobs index f388b67..4d2d7ef 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f388b6794e6f1f93b847de353f5eab8ba3e3b328 +Subproject commit 4d2d7efe93e79bafb234356484d80296ae801fea diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 1e800ac..a1afae4 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 1e800ac838504c0d2950c7aa90cdfe7bde251545 +Subproject commit a1afae4e002a3eccd7835ac898259b0690e9e61a diff --git a/3rdparty/cmocka b/3rdparty/cmocka index 672c5ce..5a4b158 160000 --- a/3rdparty/cmocka +++ b/3rdparty/cmocka @@ -1 +1 @@ -Subproject commit 672c5cee79eb412025c3dd8b034e611c1f119055 +Subproject commit 5a4b15870efa2225e6586fbb4c3af05ff0659434 diff --git a/3rdparty/fsp b/3rdparty/fsp index e7138bf..0bc2b07 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit e7138bf11508b8b82350bd17fb611b67c0c64e6b +Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 49bb67f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 49bb67f32a2e3e631ba1a9a73da1c52e1cac7fd9 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index bc0588e..8fc8e49 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit bc0588e482b1320d5739900b00a45033f5b587f4 +Subproject commit 8fc8e49a932c7a011429b333765c6b0ed09cd742 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index a3edc6e..bd0ed91 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit a3edc6ef32d09c566b7ea3555bc753458ec63039 +Subproject commit bd0ed91cb985a697033edd9fd62d322aa017e791 diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 02ba9a6..053eb2a 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 02ba9a6a362f67ccd097c285fa8a202dedd38631 +Subproject commit 053eb2ab5f89a8e2b2077fd70c9ae7ff945e440e diff --git a/3rdparty/vboot b/3rdparty/vboot index 57c0c5b..c531000 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 57c0c5be50767c3f86c648bf33e15955cc349f25 +Subproject commit c531000f851418520b6873f65c202d21f141eb84 diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 70c7d77..7906032 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -212,15 +212,18 @@ vboot_extend_pcr(ctx, 1, HWID_DIGEST_PCR); } -#define EC_EFS_BOOT_MODE_NORMAL 0x00 +#define EC_EFS_BOOT_MODE_RO 0x00 #define EC_EFS_BOOT_MODE_NO_BOOT 0x01 +#define EC_EFS_BOOT_MODE_VERIFIED 0x02 static const char *get_boot_mode_string(uint8_t boot_mode) { - if (boot_mode == EC_EFS_BOOT_MODE_NORMAL) - return "NORMAL"; + if (boot_mode == EC_EFS_BOOT_MODE_RO) + return "RO"; else if (boot_mode == EC_EFS_BOOT_MODE_NO_BOOT) return "NO_BOOT"; + else if (boot_mode == EC_EFS_BOOT_MODE_VERIFIED) + return "VERIFIED"; else return "UNDEFINED"; } @@ -255,6 +258,8 @@ if (boot_mode == EC_EFS_BOOT_MODE_NO_BOOT) ctx->flags |= VB2_CONTEXT_NO_BOOT; + else if (boot_mode == EC_EFS_BOOT_MODE_RO) + ctx->flags |= VB2_CONTEXT_EC_IN_RO; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/54099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa09dd7ae5baa1efb4e1ed4f0fe9a6803167c93 Gerrit-Change-Number: 54099 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: OEM variables support for DPTF
by Sumeet R Pawnikar (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak. Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54098 ) Change subject: ec/google/chromeec: OEM variables support for DPTF ...................................................................... ec/google/chromeec: OEM variables support for DPTF This adds OEM variables support for DPTF to notify the change. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/ec_dptf_helpers.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/54098/1 diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 631f16e..805a12c 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -15,6 +15,7 @@ enum { TRIP_POINTS_CHANGED_EVENT = 0x81, THERMAL_EVENT = 0x90, + ODVP_CHANGED_EVENT = 0x88, }; /* EC constants */ @@ -124,6 +125,17 @@ acpigen_pop_len(); /* Method _FSL */ } +static void write_ietm_odvp(const struct device *ec) +{ + acpigen_write_name("ODVP"); + acpigen_write_package(6); + acpigen_write_integer(0); + + /* Notify DPTF about ODVP change */ + acpigen_notify("ODVP", ODVP_CHANGED_EVENT); + acpigen_pop_len(); +} + /* * Emit code to execute if the policy is enabled after this function is called, and also * remember to manually add a acpigen_pop_len() afterwards! @@ -283,6 +295,12 @@ } acpigen_pop_len(); /* Method */ + + /* ODVE */ + acpigen_write_method_serialized("ODVE", 0); + acpigen_notify("ODVP", ODVP_CHANGED_EVENT); + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ } @@ -302,6 +320,13 @@ acpigen_pop_len(); /* Scope */ } +static void write_ietm_methods(const struct device *ec) +{ + dptf_write_scope(DPTF_IETM); + write_ietm_odvp(ec); + acpigen_pop_len(); /* Scope */ +} + static void write_thermal_methods(const struct device *ec, enum dptf_participant participant, int tsr_index) { @@ -354,6 +379,7 @@ write_dppm_methods(ec); write_charger_methods(ec); write_fan_methods(ec); + write_ietm_methods(ec); for (p = DPTF_TEMP_SENSOR_0, i = 0; p <= DPTF_TEMP_SENSOR_3; ++p, ++i) write_thermal_methods(ec, p, i); -- To view, visit https://review.coreboot.org/c/coreboot/+/54098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79fbf00521d54e66b6cd7d95b026a76fd3a4394b Gerrit-Change-Number: 54098 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST: To test OEM variable functionality
by Sumeet R Pawnikar (Code Review) 12 May '21

12 May '21

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51937 to look at the new patch set (#2). Change subject: TEST: To test OEM variable functionality ...................................................................... TEST: To test OEM variable functionality Test OEM variable functionality Change-Id: I65e7245d8e4dadaa3ad9ea14d606940ca364e5a1 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/51937/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e7245d8e4dadaa3ad9ea14d606940ca364e5a1 Gerrit-Change-Number: 51937 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021