coreboot-gerrit May 2021

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Change in coreboot[master]: util: Add DDR4 generic SPD for Samsung K4AAG165WB-BCWE 16Gb
by Kevin Chiu (Code Review) 13 May '21

13 May '21

Kevin Chiu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/54231 ) Change subject: util: Add DDR4 generic SPD for Samsung K4AAG165WB-BCWE 16Gb ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/54231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11cc8e89eb0ba198235a10726e7193108675268e Gerrit-Change-Number: 54231 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/mediatek/mt8195: Initialize DRAM in romstage
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54229 ) Change subject: soc/mediatek/mt8195: Initialize DRAM in romstage ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54229/comment/c09136ce_8526ec64 PS1, Line 9: and porting DRAM fast-k. this is not included in this patch? or is it? File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54229/comment/45f8d61a_59d56159 PS1, Line 31: ../common/memory_test.c move to next line. https://review.coreboot.org/c/coreboot/+/54229/comment/59afc53d_29a88188 PS1, Line 61: BL31_MAKEARGS += PLAT=mt8195 this should not be included in this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/54229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Gerrit-Change-Number: 54229 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:20:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor/mediatek: Add MT8195 dram initialization code
by Yu-Ping Wu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Rex-BC Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54230 ) Change subject: vendor/mediatek: Add MT8195 dram initialization code ...................................................................... Patch Set 1: (1 comment) File src/vendorcode/mediatek/mt8195/dramc/Makefile.inc: PS1: Error: Check that source files are not executable (lint-stable-012-executable-bit): File src/vendorcode/mediatek/mt8195/dramc/Makefile.inc has one or more executable bits set in the file permissions. test failed -- To view, visit https://review.coreboot.org/c/coreboot/+/54230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Gerrit-Change-Number: 54230 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:18:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendor/mediatek: Add MT8195 dram initialization code
by Hung-Te Lin (Code Review) 13 May '21

13 May '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54230 ) Change subject: vendor/mediatek: Add MT8195 dram initialization code ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: File src/vendorcode/mediatek/mt8195/dramc/Makefile.inc has one or more executable bits set in the file permissions. We should still fix this. -- To view, visit https://review.coreboot.org/c/coreboot/+/54230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Gerrit-Change-Number: 54230 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:17:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Initialize DRAM in romstage
by Yu-Ping Wu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54229 ) Change subject: soc/mediatek/mt8195: Initialize DRAM in romstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Gerrit-Change-Number: 54229 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 13 May 2021 08:16:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Paul Menzel (Code Review) 13 May '21

13 May '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/53926/comment/c002fee3_9d9d28c3 PS1, Line 7: cpu/x86/smm: Fix typo > Ack Yes, but I like commit messages, where you do not need to look at the diff. For typos I always wonder, how “serious” they are. -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: update DRAM table for gumboz/dirinboz
by Kevin Chiu (Code Review) 13 May '21

13 May '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54250 ) Change subject: mb/google/zork: update DRAM table for gumboz/dirinboz ...................................................................... mb/google/zork: update DRAM table for gumboz/dirinboz Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d --- M src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc M src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt 4 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/54250/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt index 5a6541f..974addb 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -16,3 +16,4 @@ K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 H5ANAG6NCJR-XNC +K4AAG165WB-BCWE diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc index 6d8a906..6d8e749 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC, K4AAG165WB-BCWE SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt index d6d5d09..9f9949c 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -8,3 +8,4 @@ K4AAG165WA-BCTD 9 (1001) K4AAG165WA-BCWE 10 (1010) H5ANAG6NCJR-XNC 0 (0000) +K4AAG165WB-BCWE 0 (0000) diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt index e5cd7e2..f220073 100644 --- a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -17,3 +17,4 @@ K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 H5ANAG6NCJR-XNC +K4AAG165WB-BCWE -- To view, visit https://review.coreboot.org/c/coreboot/+/54250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Gerrit-Change-Number: 54250 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by Tao Xia (Code Review) 13 May '21

13 May '21

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/Codec ...................................................................... mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/Codec Configure I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). Measured I2C frequency just as below after tuning: touchpad:387 kHz touchpanel:388 kHz audio codec RT5682:391 kHz BUG=b:187555396 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 --- M src/mainboard/google/dedede/variants/blipper/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/54249/1 diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index df3f9dd..40e35d7 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -21,18 +21,36 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[1] = { .speed = I2C_SPEED_FAST, }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, .i2c[4] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } }, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Dtrain Hsu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Dtrain Hsu, Henry Sun, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Henry Sun, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54057 to look at the new patch set (#2). Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/Makefile.inc M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb M src/mainboard/google/dedede/variants/cret/variant.c 5 files changed, 32 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/54057/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util: Add DDR4 generic SPD for Samsung K4AAG165WB-BCWE 16Gb
by Kevin Chiu (Code Review) 13 May '21

13 May '21

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54231 ) Change subject: util: Add DDR4 generic SPD for Samsung K4AAG165WB-BCWE 16Gb ...................................................................... util: Add DDR4 generic SPD for Samsung K4AAG165WB-BCWE 16Gb Add SPD support for Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I11cc8e89eb0ba198235a10726e7193108675268e --- M util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/54231/1 diff --git a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt index 03c6630..3a0ea9d 100644 --- a/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt +++ b/util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt @@ -227,6 +227,22 @@ "packageBusWidth": 16, "ranksPerPackage": 1 } + }, + { + // Datasheet Revision: Rev. 0.5, Feb. 2019 + "name": "K4AAG165WB-BCWE", + "attribs": { + "speedMTps": 3200, + "CL_nRCD_nRP": 22, + "capacityPerDieGb": 16, + "diesPerPackage": 1, + "packageBusWidth": 16, + "ranksPerPackage": 1, + // Table 57 - 16Gb + "TRFC1MinPs": 350000, + "TRFC2MinPs": 260000, + "TRFC4MinPs": 160000 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/54231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11cc8e89eb0ba198235a10726e7193108675268e Gerrit-Change-Number: 54231 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021