coreboot-gerrit May 2021

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Change in coreboot[master]: soc/mediatek/mt8195: Initialize DRAM in romstage
by Rex-BC Chen (Code Review) 13 May '21

13 May '21

Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54229 to look at the new patch set (#3). Change subject: soc/mediatek/mt8195: Initialize DRAM in romstage ...................................................................... soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage. Add DRAM fast calibration support Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/dramc_soc.h D src/soc/mediatek/mt8195/include/soc/emi.h 4 files changed, 66 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/54229/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Gerrit-Change-Number: 54229 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Dtrain Hsu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Tim Wawrzynczak, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Henry Sun, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54057 to look at the new patch set (#3). Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/Makefile.inc M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb M src/mainboard/google/dedede/variants/cret/variant.c 5 files changed, 31 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/54057/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CO...
by Dtrain Hsu (Code Review) 13 May '21

13 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Tim Wawrzynczak, Karthik Ramasubramanian. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54057 ) Change subject: mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIG ...................................................................... Patch Set 2: (4 comments) Patchset: PS1: > @Furquan/Tim, Is it ok to enable fw_config in SMM stage? I am not sure if it was intentionally not e […] If enable fw_config in SMM mode has concern, I think we could remove fw_config detection on SMM mode and still control the Lte power off sequence. File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/54057/comment/2e5f768d_6c5548d0 PS1, Line 188: smm-$(CONFIG_FW_CONFIG) += fw_config.c > Please move it to a separate change of its own. […] Done File src/mainboard/google/dedede/variants/cret/gpio.c: https://review.coreboot.org/c/coreboot/+/54057/comment/61f75af3_d2e22a8c PS1, Line 122: > Instead of maintaining 2 large tables, can you please check if this approach works for you keeping t […] The test result is the same with b/187797408#comment1 File src/mainboard/google/dedede/variants/cret/overridetree.cb: https://review.coreboot.org/c/coreboot/+/54057/comment/a4951697_f83d433a PS1, Line 88: probe LTE LTE_PRESENT > Just want to remind that this works as long as you dont re-use the same USB port for a different use […] The USB port is only for LTE now on Cret. Thank you for remind. -- To view, visit https://review.coreboot.org/c/coreboot/+/54057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Gerrit-Change-Number: 54057 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:36:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE
by Rex-BC Chen (Code Review) 13 May '21

13 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53898 to look at the new patch set (#6). Change subject: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE Enable ATF configuration to support multi-core. TEST=boot to kernel with multi-core support. BUG=b:177593590 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/53898/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/53898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Gerrit-Change-Number: 53898 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Initialize DRAM in romstage
by Rex-BC Chen (Code Review) 13 May '21

13 May '21

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54229 to look at the new patch set (#2). Change subject: soc/mediatek/mt8195: Initialize DRAM in romstage ...................................................................... soc/mediatek/mt8195: Initialize DRAM in romstage Initialize DRAM in romstage. Add DRAM fast calibration support Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.com> --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/dramc_soc.h D src/soc/mediatek/mt8195/include/soc/emi.h 4 files changed, 65 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/54229/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Gerrit-Change-Number: 54229 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Angel Pons (Code Review) 13 May '21

13 May '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/53926/comment/6dcfa8ed_66594e82 PS1, Line 7: cpu/x86/smm: Fix typo > Yes, but I like commit messages, where you do not need to look at the diff. […] Specifying that the typo is in a comment lets people (e.g. reviewers) know that the change is supposed to not impact functionality. Some people like to describe one-line code changes as "typos", and these changes can sometimes have a huge impact. Given that editing the commit message is very easy to do in Gerrit and preserves the review scores, I believe that disregarding Paul's suggestion was uncalled for. But it's too late now. -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 13 May 2021 08:31:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/Tianocore: Update default build target, simplify build options
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54019 ) Change subject: payloads/Tianocore: Update default build target, simplify build options ...................................................................... payloads/Tianocore: Update default build target, simplify build options Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig option since it applied only to CorebootPayloadPkg. Clean up the Makefile now that we're only building from a single Tianocore package/target. Test: build/boot qemu Q35 target with both UefiPayload and Upstream options. Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/payloads.md M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 4 files changed, 24 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/Documentation/payloads.md b/Documentation/payloads.md index eee841e..7f4c08c 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -21,7 +21,7 @@ implementation of the UEFI Specifications that modern firmware for PCs is based on. There were various projects in the past to make it suitable as a coreboot payload, but these days this function is available directly in the -CorebootPayloadPkg part of its source tree. +UefiPayloadPkg part of its source tree. ## GRUB2 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9b4e708..e30f570 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -143,10 +143,9 @@ CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \ CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \ - CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ - CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ + CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 87b6e15..e53be16 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -4,26 +4,26 @@ string "Tianocore binary" default "payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd" help - The result of a corebootPkg build + The result of a UefiPayloadPkg build choice prompt "Tianocore payload" - default TIANOCORE_COREBOOTPAYLOAD + default TIANOCORE_UEFIPAYLOAD help - Select which type of payload Tianocore will build (default is CorebootPayload) - CorebootPayload: MrChromebox's customized version of Tianocore which works on most - (all?) x86_64 devices - UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2 - -config TIANOCORE_COREBOOTPAYLOAD - bool "CorebootPayload" - help - Select this option to build using MrChromebox's custom Tianocore tree - i.e. a version of Tianocore that builds without any errors and just works. + Select which type of payload Tianocore will build (default is UefiPayload) + UefiPayload: MrChromebox's customized fork of Tianocore which works on most + x86_64 devices + Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2 config TIANOCORE_UEFIPAYLOAD bool "UEFIPayload" help + Select this option to build using MrChromebox's custom Tianocore fork, + which incorporates fixes/improvements from System 76's and 9elements' trees. + +config TIANOCORE_UPSTREAM + bool "Upstream" + help Select this option if you want to use upstream EDK2 to build Tianocore. endchoice @@ -76,11 +76,6 @@ endchoice -config TIANOCORE_USE_8254_TIMER - bool "TianoCore 8254 Timer" - help - Use 8254 Timer for legacy support. - config TIANOCORE_BOOTSPLASH_IMAGE bool "Use a custom bootsplash image" help diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 7cd34f1..ad0328a 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -6,18 +6,15 @@ project_name=Tianocore project_dir=$(CURDIR)/tianocore project_git_repo=https://github.com/mrchromebox/edk2 -project_git_branch=coreboot_fb +project_git_branch=uefipayloadpkg upstream_git_repo=https://github.com/tianocore/edk2 -ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y) -bootloader=UefiPayloadPkg -logo_pkg=MdeModulePkg build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE + +ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y) TAG=upstream/master else -bootloader=CorebootPayloadPkg -logo_pkg=CorebootPayloadPkg -# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch +# STABLE revision is MrChromebox's UefiPayloadPkg (ueifpayloadpkg) branch TAG=origin/$(project_git_branch) endif @@ -33,23 +30,15 @@ BUILD_TYPE=RELEASE endif -ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y) -TIMER=-DUSE_HPET_TIMER -endif - TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) -ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +ARCH=-a IA32 else -ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -endif -else -ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc +ARCH=-a IA32 -a X64 endif -BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor) +BUILD_STR=-q $(ARCH) -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) all: clean build @@ -93,9 +82,9 @@ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \ + $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ *) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \ + $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ esac \ fi; \ cd $(project_dir); \ @@ -108,7 +97,7 @@ fi; \ build $(BUILD_STR); \ mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ - git checkout $(logo_pkg)/Logo/Logo.bmp > /dev/null 2>&1 || true + git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/54019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e Gerrit-Change-Number: 54019 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrik Tesarik <depate(a)das-labor.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_whl: Add libgfxinit support
by Angel Pons (Code Review) 13 May '21

13 May '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46627 ) Change subject: mb/purism/librem_whl: Add libgfxinit support ...................................................................... mb/purism/librem_whl: Add libgfxinit support Only the DisplayPort output is working as of now. The HDMI 2.0 output is provided by a Parade DP175 LSPCON, which is internally connected to DP2. LSPCON setup in libgfxinit is missing as of now, but will be added soon. Change-Id: I0da26fef304583eec0375eee2082a9d2ebe27292 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/purism/librem_whl/Kconfig M src/mainboard/purism/librem_whl/Makefile.inc A src/mainboard/purism/librem_whl/gma-mainboard.ads 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46627/1 diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig index bc25fb5..ea79d90 100644 --- a/src/mainboard/purism/librem_whl/Kconfig +++ b/src/mainboard/purism/librem_whl/Kconfig @@ -6,6 +6,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA_VERB diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc index ba157df..0725df5 100644 --- a/src/mainboard/purism/librem_whl/Makefile.inc +++ b/src/mainboard/purism/librem_whl/Makefile.inc @@ -4,4 +4,6 @@ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_whl/gma-mainboard.ads b/src/mainboard/purism/librem_whl/gma-mainboard.ads new file mode 100644 index 0000000..5494485 --- /dev/null +++ b/src/mainboard/purism/librem_whl/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- DisplayPort connector + DP2, -- HDMI connector through Parade DP175 LSPCON + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/46627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da26fef304583eec0375eee2082a9d2ebe27292 Gerrit-Change-Number: 46627 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS
by Patrick Georgi (Code Review) 13 May '21

13 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54058 ) Change subject: mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS ...................................................................... mb/prodrive/hermes: Disable ACPI S3 and S4 with SPS Hermes can be used with either CSME or SPS firmware. However, the SPS (Server Platform Services) firmware does not support ACPI S3 and S4 sleep states, and coreboot should not report S3 and S4 as supported. Add a Kconfig option to be selected when building coreboot to use with SPS firmware, which allows disabling ACPI S3 and S4 sleep state support. Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54058 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/prodrive/hermes/Kconfig 1 file changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/prodrive/hermes/Kconfig b/src/mainboard/prodrive/hermes/Kconfig index 178acce..ac497e6 100644 --- a/src/mainboard/prodrive/hermes/Kconfig +++ b/src/mainboard/prodrive/hermes/Kconfig @@ -14,10 +14,18 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_HDA_VERB select ONBOARD_VGA_IS_PRIMARY - select HAVE_ACPI_RESUME + select HAVE_ACPI_RESUME if !HERMES_USES_SPS_FIRMWARE + select DISABLE_ACPI_HIBERNATE if HERMES_USES_SPS_FIRMWARE if BOARD_PRODRIVE_HERMES_BASEBOARD +config HERMES_USES_SPS_FIRMWARE + bool "Build for use with SPS (Server Platform Services) firmware" + help + Depending on the intended use case, the Hermes mainboard can use either + CSME or SPS firmware SKUs. Choose this option if using SPS firmware, as + SPS doesn't support ACPI S3 and S4 sleep states. + config MAINBOARD_FAMILY string default "PRODRIVE_HERMES_SERIES" -- To view, visit https://review.coreboot.org/c/coreboot/+/54058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec Gerrit-Change-Number: 54058 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: update DRAM table for gumboz/dirinboz
by Kevin Chiu (Code Review) 13 May '21

13 May '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54250 to look at the new patch set (#2). Change subject: mb/google/zork: update DRAM table for gumboz/dirinboz ...................................................................... mb/google/zork: update DRAM table for gumboz/dirinboz Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d --- M src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc M src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt M src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc M src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt 6 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/54250/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Gerrit-Change-Number: 54250 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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