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Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/52058/5
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52058 )
Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52058/comment/ab685a53_833d199d
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
:
: On Cezanne, the PSP modifies these registers such that the eSPI
> Why is the PSP writing to port80?
The PSP writes port 80s to signal where it in the boot processes. i.e., sign of life, memory training, etc. It uses 16 MHz and single IO mode. We don't currently get these eport 80s on the ChromeEC. See b/181598456.
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Change subject: soc/amd: Make espi_configure_decodes private
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/cezanne/early_fch.c:
https://review.coreboot.org/c/coreboot/+/52059/comment/c784d134_65f8d8ac
PS4, Line 71: espi_clear_decodes
> Given that we are doing a complete reset of the eSPI controller in `espi_setup()` anyways, I think w […]
Agree. I didn't want to touch the orignal CLs since they have +2. I'll push a follow up with the change.
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Change subject: soc/intel/xeon_sp: More PCU locks
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Patch Set 1: Code-Review+1
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Change subject: drivers/intel/fsp1_1: Drop dead MMA code
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Patch Set 2: Code-Review+2
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Change subject: soc/amd: Make espi_configure_decodes private
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/cezanne/early_fch.c:
https://review.coreboot.org/c/coreboot/+/52059/comment/c453c581_6a8b9c35
PS4, Line 71: espi_clear_decodes
Given that we are doing a complete reset of the eSPI controller in `espi_setup()` anyways, I think we should just move this to `espi_setup()` as well.
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Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52058/comment/22de2e8c_8134694a
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
:
: On Cezanne, the PSP modifies these registers such that the eSPI
> eSPI is interesting because the PSP configures the controller so it can write port80s before jumping […]
Why is the PSP writing to port80?
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