coreboot-gerrit April 2021

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Change in coreboot[master]: lib: Add obvious definition for `calloc`
by Tim Wawrzynczak (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51949 ) Change subject: lib: Add obvious definition for `calloc` ...................................................................... Patch Set 9: (1 comment) File tests/lib/malloc-test.c: https://review.coreboot.org/c/coreboot/+/51949/comment/bc845f0f_b926c44d PS8, Line 148: int > size_t ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Gerrit-Change-Number: 51949 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:22:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add obvious definition for `calloc`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51949 ) Change subject: lib: Add obvious definition for `calloc` ...................................................................... Patch Set 8: Code-Review+1 (1 comment) File tests/lib/malloc-test.c: https://review.coreboot.org/c/coreboot/+/51949/comment/ffdd75ad_fbc62c95 PS8, Line 148: int size_t ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Gerrit-Change-Number: 51949 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:19:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Move early GPIO config earlier
by Tim Wawrzynczak (Code Review) 02 Apr '21

02 Apr '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52062 ) Change subject: mb/google/brya: Move early GPIO config earlier ...................................................................... mb/google/brya: Move early GPIO config earlier The recent refactor of console UART GPIOs to mainboard's bootblock caused brya boards to lose the first ~5 lines of the logs from bootblock. Rename bootblock_mainboard_init to bootblock_mainboard_early_init so that the UART pads will be ready by the time the console is initialized. BUG=b:184319828 TEST=First lines from report_platform.c are now seen in UART output Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 --- M src/mainboard/google/brya/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/52062/1 diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index 817dd0f..1815615 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <bootblock_common.h> -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; -- To view, visit https://review.coreboot.org/c/coreboot/+/52062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Gerrit-Change-Number: 52062 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 ) Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/51159/comment/9a5dc235_b5a2d92b PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ > Sorry I can make the comment a little more clear, this is how Intel does the mapping for PIC-mode IRQs (IRQ11 for INTA,INTC,INTD, and IRQ10 for INTB). I'm not convinced. To allow the mapping we provide for the APIC mode, FSP has to configure PIR registers (ITSS PCR) and then there is no direct mapping from pins to PIRQs guaranteed. Or do I miss something in that direction? -- To view, visit https://review.coreboot.org/c/coreboot/+/51159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Gerrit-Change-Number: 51159 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:18:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: spd.h: Move `DIMMx` macros to i440bx/raminit.h
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52061 ) Change subject: spd.h: Move `DIMMx` macros to i440bx/raminit.h ...................................................................... spd.h: Move `DIMMx` macros to i440bx/raminit.h These macros aren't needed anywhere else, so reduce their visibility. Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/spd.h M src/northbridge/intel/i440bx/raminit.h 2 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/52061/1 diff --git a/src/include/spd.h b/src/include/spd.h index 9695932..ec5296e 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -197,16 +197,6 @@ #define MODULE_BUFFERED 1 #define MODULE_REGISTERED 2 -/* DIMM SPD addresses */ -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - /* Byte 3: Module type information */ #define SPD_UNDEFINED 0x00 #define SPD_RDIMM 0x01 diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 1bd5ab6..d2d1729 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -6,6 +6,12 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 +/* DIMM SPD addresses */ +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 + void enable_spd(void); void disable_spd(void); void sdram_initialize(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/52061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Gerrit-Change-Number: 52061 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: spd.h: Remove unused definitions
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51900 to look at the new patch set (#4). Change subject: spd.h: Remove unused definitions ...................................................................... spd.h: Remove unused definitions These definitions are unused and not particularly useful. Drop them. Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/spd.h 1 file changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/51900/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Gerrit-Change-Number: 51900 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/i945: Refactor `dump_spd_registers` function
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Nico Huber, Stefan Reinauer, Angel Pons, Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Paul Menzel, Stefan Reinauer, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51899 to look at the new patch set (#4). Change subject: nb/intel/i945: Refactor `dump_spd_registers` function ...................................................................... nb/intel/i945: Refactor `dump_spd_registers` function Use the mainboard-provided SPD map and skip unused addresses. Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/romstage.c 3 files changed, 10 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/51899/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Gerrit-Change-Number: 51899 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
by Furquan Shaikh (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52056 ) Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/52056/comment/e4a07f0f_8d8aa053 PS2, Line 475: return -1; > I wanted to leave all the evidence in case of a failure. […] I think it is okay to leave the bit as is in case of failure. I wanted to make sure this was intentional. Also, I am curious, is the bit being cleared in successful case because we are seeing unexpected behavior later because of bit remaining set? I see there is already a call to `espi_clear_status()` at the start of this function to ensure we start clean state before a new transaction. So, the motivation behind this change wasn't very clear to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/52056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Gerrit-Change-Number: 52056 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:09:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: More PCU locks
by build bot (Jenkins) (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52060 ) Change subject: soc/intel/xeon_sp: More PCU locks ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/52060/comment/8adf528b_6d88786e PS1, Line 124: pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/52060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8211977e87109a91790a4070454fc561aa761b Gerrit-Change-Number: 52060 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:02:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: More PCU locks
by Marc Jones (Code Review) 02 Apr '21

02 Apr '21

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52060 ) Change subject: soc/intel/xeon_sp: More PCU locks ...................................................................... soc/intel/xeon_sp: More PCU locks Add the following locks as recommended by the Intel docs: DRAM_POWER_INFO_LOCK PCU_CR3_FLEX_RATIO_LOCK TURBO_ACTIVATION_RATIO_LOCK PCU_CR0_PMAX_LOCK Change-Id: I8d8211977e87109a91790a4070454fc561aa761b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 4 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52060/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index a223542..500f83e 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -121,6 +121,8 @@ const struct device *cr0_dev = PCU_DEV_CR0(bus); pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); + pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); + /* configure PCU_CR1_FUN csrs */ const struct device *cr1_dev = PCU_DEV_CR1(bus); @@ -129,10 +131,12 @@ /* configure PCU_CR2_FUN csrs */ const struct device *cr2_dev = PCU_DEV_CR2(bus); pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); + pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); /* configure PCU_CR3_FUN csrs */ const struct device *cr3_dev = PCU_DEV_CR3(bus); pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); } } diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 122a376..7b16945 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -25,11 +25,15 @@ #define PCU_CR0_FUN 0 #define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 +#define TURBO_ACTIVATION_RATIO_LOCK BIT(31) #define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK BIT(31) +#define P_STATE_LIMITS_LOCK BIT(31) #define PCU_CR0_PACKAGE_RAPL_LIMIT_LWR 0xe8 #define PCU_CR0_PACKAGE_RAPL_LIMIT_UPR (PCU_CR0_PACKAGE_RAPL_LIMIT_LWR + 4) -#define PKG_PWR_LIM_LOCK_UPR BIT(31) +#define PKG_PWR_LIM_LOCK_UPR BIT(31) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31) #define PCU_CR1_FUN 1 #define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) @@ -60,13 +64,18 @@ #define PCU_CR2_FUN 2 #define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 +#define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) +#define DRAM_POWER_INFO_LOCK_UPR BIT(31) #define PCU_CR2_DRAM_PLANE_POWER_LIMIT 0xf0 #define PP_PWR_LIM_LOCK BIT(31) #define PCU_CR3_FUN 3 #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 -#define TDP_LOCK BIT(31) +#define TDP_LOCK BIT(31) +#define PCU_CR3_FLEX_RATIO 0xa0 +#define OC_LOCK BIT(20) #if !defined(__SIMPLE_DEVICE__) #define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index c7af810..96239ba 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -26,11 +26,18 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44 +#if !defined(__SIMPLE_DEVICE__) +#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#else +#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#endif + #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR1_FUN 1 #define PCU_CR0_FUN 0 +#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 #define P_STATE_LIMITS_LOCK_SHIFT 31 @@ -40,6 +47,8 @@ #define PCU_CR0_CURRENT_CONFIG 0xf8 #define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ #define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR0_PMAX 0xf0 +#define PMAX_LOCK BIT(31) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index baf5102..ce0b1a6 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -318,6 +318,9 @@ if (timedout) die("BIOS RESET CPL3 timed out.\n"); + /* Set PMAX_LOCK - must be set before RESET CPL4 */ + pci_or_config32(PCU_DEV_CR0(bus), PCU_CR0_PMAX, PMAX_LOCK); + /* update RST_CPL4, PCODE_INIT_DONE4 */ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); -- To view, visit https://review.coreboot.org/c/coreboot/+/52060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8211977e87109a91790a4070454fc561aa761b Gerrit-Change-Number: 52060 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021