Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52069 )
Change subject: device/Kconfig: Adapt PCIEXP_HOTPLUG_BUSES
......................................................................
device/Kconfig: Adapt PCIEXP_HOTPLUG_BUSES
The default of 32 buses per hotplug bridge is rather high. Especially
for platforms that limit MMConf space to 64 buses: they run out of
numbers if there is more than a single hotplug bridge.
Lower the default to
* 8 if MMConf is limitted to 64 or less buses,
* 16 if MMConf is limitted to 128 or less buses.
Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/device/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52069/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 1bfc34a..63b7d6c 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -626,6 +626,8 @@
config PCIEXP_HOTPLUG_BUSES
int "PCI Express Hotplug Buses"
+ default 8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 64
+ default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
default 32
help
This is the number of buses allocated for hotplug PCI express
--
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Gerrit-Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52066 )
Change subject: util/kconfig_lint: Drop exception for paths without quotes
......................................................................
util/kconfig_lint: Drop exception for paths without quotes
The tree is clean at the moment.
Change-Id: I1be3b6c2f3b54b5c10ad3d5c6f0a6fd7e490c6bc
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M util/lint/kconfig_lint
1 file changed, 0 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52066/1
diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint
index 2341976..43a3ca6 100755
--- a/util/lint/kconfig_lint
+++ b/util/lint/kconfig_lint
@@ -993,11 +993,6 @@
handle_expressions( $1, $inside_config, $filename, $line_no );
handle_expressions( $2, $inside_config, $filename, $line_no );
}
-
- # work around kconfig spec violation for now - paths not in quotes
- elsif ( $exprline =~ /^\s*([A-Za-z0-9_\-\/]+)\s*$/ ) { # <symbol> (1)
- return;
- }
else {
show_error("Unrecognized expression '$exprline' in $filename line $line_no.");
}
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52064 )
Change subject: soc/amd: Make espi_clear_decodes private
......................................................................
soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
3 files changed, 3 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52064/1
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index 0e351a9..5dca211 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -67,8 +67,6 @@
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
- if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
- espi_clear_decodes();
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
- }
}
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index f5e7d31..435b81f 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -101,13 +101,6 @@
int espi_open_mmio_window(uint32_t base, size_t size);
/*
- * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing
- * the decodes, or if something else has previously setup decode windows that conflict
- * with the windows that coreboot needs.
- */
-void espi_clear_decodes(void);
-
-/*
* In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading
* SPIBASE. This is required for cases where verstage runs on PSP.
*/
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0b690b8..f120082 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -98,7 +98,7 @@
return -1;
}
-void espi_clear_decodes(void)
+static void espi_clear_decodes(void)
{
unsigned int idx;
@@ -894,6 +894,7 @@
espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
espi_write32(ESPI_SLAVE0_INT_EN, 0);
espi_clear_status();
+ espi_clear_decodes();
/*
* Boot sequence: Step 1
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Change subject: soc/amd: Make espi_configure_decodes private
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/52059/comment/68b4175e_56058f9f
PS4, Line 301: void
Made this return an error code since it can fail.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Make espi_configure_decodes private
......................................................................
soc/amd: Make espi_configure_decodes private
This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
M src/soc/amd/picasso/early_fch.c
M src/soc/amd/picasso/psp_verstage/fch.c
5 files changed, 15 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52059/5
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Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/52058/comment/2659b131_79ee77a1
PS4, Line 891: espi_write32(ESPI_SLAVE0_INT_STS, 0xFFFFFFFF);
I switched this to use `espi_clear_status`.
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/52058/5
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