coreboot-gerrit April 2021

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Change in coreboot[master]: soc/amd/common/espi: Add missing eSPI register definitions
by Furquan Shaikh (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52057 ) Change subject: soc/amd/common/espi: Add missing eSPI register definitions ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Gerrit-Change-Number: 52057 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:35:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Make espi_configure_decodes private
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52059 to look at the new patch set (#4). Change subject: soc/amd: Make espi_configure_decodes private ...................................................................... soc/amd: Make espi_configure_decodes private This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/psp_verstage/fch.c 5 files changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52059/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Gerrit-Change-Number: 52059 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52056 to look at the new patch set (#4). Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion ...................................................................... soc/amd/common/espi: Clear DNCMD_COMPLETE on completion Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/52056/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Gerrit-Change-Number: 52056 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 15: Code-Review+1 (1 comment) File src/southbridge/intel/common/acpi_pirq_gen.h: https://review.coreboot.org/c/coreboot/+/50857/comment/f957a9b6_a96c70e1 PS15, Line 53: unsigned int nit: use `enum pirq` instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:30:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: Make espi_configure_decodes private
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52059 to look at the new patch set (#3). Change subject: soc/amd: Make espi_configure_decodes private ...................................................................... soc/amd: Make espi_configure_decodes private This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/psp_verstage/fch.c 5 files changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52059/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Gerrit-Change-Number: 52059 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52056 ) Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/52056/comment/8a324db4_38ec251b PS2, Line 475: return -1; > I think it is okay to leave the bit as is in case of failure. […] It wasn't causing any problems. I'm only clearing it because I was looking at the eSPI registers before we jumped to the payload and noticed that ESPI_STATUS_DNCMD_COMPLETE was still set and caught me by surprise. -- To view, visit https://review.coreboot.org/c/coreboot/+/52056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Gerrit-Change-Number: 52056 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi: Reset eSPI registers to known state
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52058 ) Change subject: soc/amd/common/espi: Reset eSPI registers to known state ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52058/comment/6e60b970_9020bb19 PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR. : : On Cezanne, the PSP modifies these registers such that the eSPI > I am not against this change, but I think the PSP should not be touching any of these bits. […] eSPI is interesting because the PSP configures the controller so it can write port80s before jumping to the x86. If the eSPI controller is following the initialization sequence in `55861 - AMD System Peripheral Bus Overview` then it will have to touch these registers. -- To view, visit https://review.coreboot.org/c/coreboot/+/52058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Gerrit-Change-Number: 52058 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi: Add missing eSPI register definitions
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52057 ) Change subject: soc/amd/common/espi: Add missing eSPI register definitions ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/52057/comment/feb1bbfa_2a021f80 PS2, Line 329: irq > (irq) Done https://review.coreboot.org/c/coreboot/+/52057/comment/956a688a_6f6edaa5 PS2, Line 333: irq > (irq) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Gerrit-Change-Number: 52057 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:29:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi: Add missing eSPI register definitions
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52057 to look at the new patch set (#3). Change subject: soc/amd/common/espi: Add missing eSPI register definitions ...................................................................... soc/amd/common/espi: Add missing eSPI register definitions These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/52057/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Gerrit-Change-Number: 52057 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add obvious definition for `calloc`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51949 ) Change subject: lib: Add obvious definition for `calloc` ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720 Gerrit-Change-Number: 51949 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 18:29:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2021