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Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/52056/comment/5548c4ae_f3d6a130
PS2, Line 475: return -1;
> What about this case?
I wanted to leave all the evidence in case of a failure. I can clear it here too if you don't think it will cause confusion.
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Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52058/comment/c63b7499_25c30304
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
:
: On Cezanne, the PSP modifies these registers such that the eSPI
I am not against this change, but I think the PSP should not be touching any of these bits. Else, we will have a lot of problems ensuring every controller is first configured to reset state.
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Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/pm/pmlib.c:
https://review.coreboot.org/c/coreboot/+/51924/comment/db528f55_2f070835
PS3, Line 9: PWR_FAIL_INIT
> By default this bit is reset. […]
Can you please add that as a comment?
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Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/52056/comment/d6790bd7_a9a11410
PS2, Line 475: return -1;
What about this case?
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Change subject: soc/amd/cezanne: Set Power state after power failure
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52049/comment/7f2fdd41_541ca2fc
PS2, Line 13: Guybrush
> By default, it is power-off after power failure and SoC team is recommending the default policy in t […]
Posted a comment on the bug. I think we should understand what the impact of selecting the "default off" policy is for Chrome OS.
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Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/pm/pmlib.c:
https://review.coreboot.org/c/coreboot/+/51924/comment/f6f9b8c2_30b8288a
PS3, Line 9: PWR_FAIL_INIT
> What does this do?
By default this bit is reset. When BIOS configures the PWR_FAIL_* shadow bits, it is expected to set this bit so that the configuration takes effect.
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Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS14:
> Agreed, I am hesitant to submit without testing it on at least 1 of the older platforms. […]
Yes, we should definitely test this before pushing it in. Thanks Nico for catching the issues with previous patchset! Your input is always valuable :).
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