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Change subject: soc/ti/am335x/mmc.c: Fix memset length argument
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/cezanne: Set Power state after power failure
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52049/comment/e729dbe3_687735d4
PS2, Line 13: Guybrush
What is the policy we are implementing for guybrush? I think for Intel platforms this is power-on after failure.
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Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
File src/soc/amd/common/block/pm/pmlib.c:
https://review.coreboot.org/c/coreboot/+/51924/comment/e7902988_ca7e2933
PS3, Line 9: PWR_FAIL_INIT
What does this do?
https://review.coreboot.org/c/coreboot/+/51924/comment/c5df376a_ae6bb1cc
PS3, Line 21: state
nit: Use `CONFIG_MAINBOARD_POWER_FAILURE_STATE` directly here?
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Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52008 )
Change subject: soc/amd/cezanne: Add support to perform early EC sync
......................................................................
soc/amd/cezanne: Add support to perform early EC sync
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
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---
M src/soc/amd/cezanne/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 643b067..57c1961 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -8,12 +8,16 @@
#include <console/console.h>
#include <fsp/api.h>
#include <program_loading.h>
+#include <security/vboot/vboot_common.h>
asmlinkage void car_stage_entry(void)
{
post_code(0x40);
console_init();
+ if (CONFIG(VBOOT_EARLY_EC_SYNC))
+ vboot_sync_ec();
+
post_code(0x41);
fsp_memory_init(acpi_is_wakeup_s3());
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Change subject: soc/amd/cezanne: Set Power state after power failure
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/bootblock.c:
https://review.coreboot.org/c/coreboot/+/52049/comment/ee59d4f2_b3e4b796
PS1, Line 115: fch_early_init
> Makes sense to move it into fch_early_init since the concerned register is part of FCH::PM register […]
Done
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