coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Tim Wawrzynczak (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50857 to look at the new patch set (#15). Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... sb/intel/common: Refactor _PRT generation to support GSI-based tables Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 10 files changed, 182 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/50857/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 15 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 ) Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... Patch Set 2: -Code-Review (1 comment) File src/soc/amd/common/block/pm/pmlib.c: https://review.coreboot.org/c/coreboot/+/51924/comment/e38d0345_9bae7787 PS2, Line 21: get_option Do we have a cmos_layout.bin? Also should we check the return values? I don't like assuming that get_option won't change the state variable on a failure condition. Also never used the set_option... How are these set from userspace? -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 14:44:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common: Add ESPI_DEBUG_PRINT macro & Kconfig option
by Rob Barnes (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51750 ) Change subject: soc/amd/common: Add ESPI_DEBUG_PRINT macro & Kconfig option ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/include/amdblocks/espi.h: https://review.coreboot.org/c/coreboot/+/51750/comment/649bb9c2_58ba76d5 PS6, Line 13: } while 0 while (0) -- To view, visit https://review.coreboot.org/c/coreboot/+/51750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd76f283e37ea3acbaf68735dc1bcbd13ddab8b Gerrit-Change-Number: 51750 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 14:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne: Set Power state after power failure
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52049 ) Change subject: soc/amd/cezanne: Set Power state after power failure ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/cezanne/bootblock.c: https://review.coreboot.org/c/coreboot/+/52049/comment/0a2c32a7_104eace8 PS1, Line 115: fch_early_init Is this something we can put in fch_early_init? -- To view, visit https://review.coreboot.org/c/coreboot/+/52049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Gerrit-Change-Number: 52049 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 14:39:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 ) Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/amd/common/block/pm/pmlib.c: https://review.coreboot.org/c/coreboot/+/51924/comment/aa8c9735_931ab825 PS2, Line 42: PM_RTC_SHADOW_REG Writing to these four bits will set the value onto bits [7:4]. Software should always set bit 2 = 1. Should we set bit 2? The reset value is 0 according to the PPR. I think bit 2 is powerstate. -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 14:39:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork: update DRAM table for morphius
by Rob Barnes (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Kevin Chiu, Furquan Shaikh, Martin Roth, Keith Tzeng, Eric Peers, Aaron Durbin. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51947 ) Change subject: mb/google/zork: update DRAM table for morphius ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f Gerrit-Change-Number: 51947 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 14:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/pineview: Correct COMP register write
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51861 ) Change subject: nb/intel/pineview: Correct COMP register write ...................................................................... nb/intel/pineview: Correct COMP register write Reference code does an and-or operation with zero as or-value, reading and writing to the same address. The accessed register is 32-bit, and reference code programs bits 22, 21, 20, 16 to zero. However, coreboot code reads the value from bits 7..0 instead. Correct this. Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 7b9f410..391aa82 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1401,8 +1401,8 @@ MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5)); FOR_EACH_RCOMP_GROUP(i) { - /* FIXME: This should be an _AND_OR */ - MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71; + /* POR values are zero */ + MCHBAR8_AND(C0RCOMPCTRLx(i) + 2, ~0x71); } if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/51861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe Gerrit-Change-Number: 51861 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 ) Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/51159/comment/06e0b6df_ed412508 PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ This is tying a knot in my head... it can only be true for devices that still use PIRQs and for devices that can be configured we don't take this into account (we actually ignore it and use find_global_least_used_pirq(), right?). Maybe it's like this: if (16 <= entries[i].irq && entries[i].irq <= 23) pin_irq_map[num_devs].pic_pirq = (enum pirq)entries[i].irq - 16; else /* dooooooom */; Really not sure about the else case. My theory: If a device uses a unique IRQ, it just can't work in legacy PIC mode; if it would use a PIRQ in legacy PIC mode, how would it know when that is the case? Maybe it's time to throw it all* away? (*legacy PIC for ACPI aware OSs) Has anybody used that in the past 10..20 years? -- To view, visit https://review.coreboot.org/c/coreboot/+/51159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Gerrit-Change-Number: 51159 Gerrit-PatchSet: 7 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 13:25:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: Add function to lpc_lib to return PIRQ routing
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50858 ) Change subject: soc/intel/common: Add function to lpc_lib to return PIRQ routing ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib215fba54573c50a88aa4584442bd8d27ae017be Gerrit-Change-Number: 50858 Gerrit-PatchSet: 12 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 12:21:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/common: Refactor _PRT generation to support GSI-based tables
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50857 ) Change subject: sb/intel/common: Refactor _PRT generation to support GSI-based tables ...................................................................... Patch Set 14: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50857/comment/bc907216_6883295b PS14, Line 10: insteade Nit, *instead* Patchset: PS14: Sorry for leaving this unattended for long. Ping me to test the next iteration if necessary (I think we should test it). File src/southbridge/intel/common/acpi_pirq_gen.h: https://review.coreboot.org/c/coreboot/+/50857/comment/44682f27_f384cbbc PS14, Line 28: PIRQ_MAX = PIRQ_H, With `PIRQ_NONE` removed, this is the last valid index now. https://review.coreboot.org/c/coreboot/+/50857/comment/52535877_c340ffde PS14, Line 47: dveices *devices* https://review.coreboot.org/c/coreboot/+/50857/comment/fea8157b_d977b4e9 PS14, Line 69: PIRQ_MAX PIRQ_MAX is the last valid index, not the count of PIRQs. https://review.coreboot.org/c/coreboot/+/50857/comment/7a79e7ed_f0171648 PS14, Line 69: unsigned int gsi[PIRQ_MAX]; : char source_path[PIRQ_MAX][DEVICE_PATH_MAX]; This could be a union, just to emphasize that they are mutually exclusive. https://review.coreboot.org/c/coreboot/+/50857/comment/5f6082ac_55040a53 PS14, Line 79: num_devs This made me think for a second what it's about. I suppose it's the map length? Left this resolved first, but it really isn't the number of devices... The "physical" thing that is enumerated is the pins. File src/southbridge/intel/common/acpi_pirq_gen.c: https://review.coreboot.org/c/coreboot/+/50857/comment/24809153_4a1f2e76 PS14, Line 58: 16 This little number is nowhere to be found in the new implementation. File src/southbridge/intel/common/rcba_pirq.c: https://review.coreboot.org/c/coreboot/+/50857/comment/fceb1126_f7e176d2 PS14, Line 85: pin_irq_map[num_devs].pic_pirq = map_pirq(dev, int_pin); I don't think gen_apic_route() would be too happy if we leave .apic_gsi unset? ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/50857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Gerrit-Change-Number: 50857 Gerrit-PatchSet: 14 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 12:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021