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Change subject: include/cbfsglue.h: Use BIOS_INFO for LOG macro
......................................................................
Patch Set 1: Code-Review+1
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Change subject: Documentation/mb/ocp: Update Delta Lake documentation
......................................................................
Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51824/comment/8942138e_18db2874
PS5, Line 10: OSF (Open System Firmware) solution.
I have no idea, what the second part means. Is “parity of OSF solution” a separate item?
Patchset:
PS5:
These are great news!
File Documentation/mainboard/ocp/deltalake.md:
https://review.coreboot.org/c/coreboot/+/51824/comment/ce7822cf_04a1dfcc
PS5, Line 31: Intel.
Align below ACM as done above.
https://review.coreboot.org/c/coreboot/+/51824/comment/8ee3f813_df235d2f
PS5, Line 66: mapped to verbose, 0 to 4 and 9 would be mapped to quiet.
Use two spaces?
https://review.coreboot.org/c/coreboot/+/51824/comment/3637c132_c86d56cc
PS5, Line 103: - KM/BPM signing
Don’t use tabs for consistency?
https://review.coreboot.org/c/coreboot/+/51824/comment/b489051b_5fa12c03
PS5, Line 152: - ProcHot
I have no idea, what that means.
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Change subject: mb/google/dedede/var/storo: Modify eeprom setting for MIPI camera
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52048/comment/4a033ea0_a1d34cf9
PS1, Line 9: modifying
increasing
https://review.coreboot.org/c/coreboot/+/52048/comment/7ba4d5a8_5b280d1b
PS1, Line 9: Solve NVM not working
What does not work exactly?
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Change subject: mb/google/asurada: select mmc storage config
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52014/comment/57c7d610_403c0038
PS2, Line 10:
Please add:
> This adds X ms to the boot.
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Change subject: include/cbfsglue.h: Use BIOS_INFO for LOG macro
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Huh... why did I do that? The old commonlib/cbfs. […]
No problem, shit happens. Also you only notice it when building coreboot with the DEBUG_ERR log level. So it is not that strange that it wasn't noticed.
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Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
Patch Set 2:
(4 comments)
File src/soc/amd/common/block/pm/Kconfig:
https://review.coreboot.org/c/coreboot/+/51924/comment/11ecbdda_37d43505
PS1, Line 3: depends on
> depends on or select? i'd use select here
Marked it as "depends on" since it depends on pm_io_read8/pm_io_write8 implementation in SOC_AMD_COMMON_BLOCK_ACPIMMIO. I am seeing that the SOC_AMD_COMMON_BLOCK_ACPIMMIO is already selected in SoC. So it may end up as a redundant selection if we do it here.
File src/soc/amd/common/block/pm/pmlib.c:
https://review.coreboot.org/c/coreboot/+/51924/comment/7097999b_630e63b7
PS1, Line 5: #define PWR_FAIL_OFF 0x0 /* Always power off after power resumes */
: #define PWR_FAIL_ON 0x1 /* Always power on after power resumes */
: #define PWR_FAIL_PREV 0x3 /* Use previous setting after power resumes */
> Thanks for the inputs. I agree that this change is not fully ready. […]
Done
https://review.coreboot.org/c/coreboot/+/51924/comment/32ed1fae_3263e39a
PS1, Line 36: val |= pwr_fail;
> the ppr says that bit 2 should always be written to 1
Done
https://review.coreboot.org/c/coreboot/+/51924/comment/8b3bdc7d_3427fcdc
PS1, Line 40:
> Looks like Jenkins failed due to the extra blank line.
Done
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Change subject: soc/amd/cezanne: Set Power state after power failure
......................................................................
soc/amd/cezanne: Set Power state after power failure
Configure the power state to return to when the power is re-applied
after power failure.
BUG=b:183739671
TEST=Build and Boot to OS in Majolica and Guybrush. By default when the
power fails the device remains off even after power is re-applied. When
the POWER_ON_AFTER_POWER_FAILURE is enabled, the device powers on as
soon as the power is re-applied.
Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/bootblock.c
2 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/52049/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index d682892..6a27955 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -48,6 +48,7 @@
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
+ select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index 2447de6..47d246e 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -2,6 +2,7 @@
#include <amdblocks/amd_pci_mmconf.h>
#include <amdblocks/cpu.h>
+#include <amdblocks/pmlib.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/amd/mtrr.h>
@@ -110,5 +111,6 @@
{
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+ pm_set_power_failure_state();
fch_early_init();
}
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Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Patrick Georgi, Martin Roth, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51924
to look at the new patch set (#2).
Change subject: soc/amd/common: Handle power resume after power failure
......................................................................
soc/amd/common: Handle power resume after power failure
Introduce a power management library to handle the power resume after
power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this
library is enabled.
BUG=b:183739671
TEST=Build Guybrush and Majolica mainboard.
Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
A src/soc/amd/common/block/include/amdblocks/pmlib.h
A src/soc/amd/common/block/pm/Kconfig
A src/soc/amd/common/block/pm/Makefile.inc
A src/soc/amd/common/block/pm/pmlib.c
4 files changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51924/2
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EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52012 )
Change subject: soc/intel/alderlake:[TEST ONLY] Enable RMT
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/52012/comment/b994dc8f_83ef3bb6
PS2, Line 77:
> Is `RmtPerTask` not needed?
haha nope, I asked in the issue. From the RMT guide line it is not needed.
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