coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/shadowmountain: Add Cr50 support
by Rizwan Qureshi (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak, Sugnan Prabhu S, Paul Menzel, Aamir Bohra. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51086 ) Change subject: mb/intel/shadowmountain: Add Cr50 support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Gerrit-Change-Number: 51086 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 04:46:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add Cr50 support
by Furquan Shaikh (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak, Sugnan Prabhu S, Paul Menzel, Aamir Bohra. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51086 ) Change subject: mb/intel/shadowmountain: Add Cr50 support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33f7427d1675190f65acf14679be93546e6db69a Gerrit-Change-Number: 51086 Gerrit-PatchSet: 7 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 04:10:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add initial support for HMAT
by Jonathan Zhang (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, Subrata Banik. Hello Lance Zhao, build bot (Jenkins), Anjaneya "Reddy" Chagam, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52047 to look at the new patch set (#2). Change subject: src/acpi: Add initial support for HMAT ...................................................................... src/acpi: Add initial support for HMAT Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 116 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52047/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Gerrit-Change-Number: 52047 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/storo: Modify eeprom setting for MIPI camera
by Tao Xia (Code Review) 02 Apr '21

02 Apr '21

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52048 ) Change subject: mb/google/dedede/var/storo: Modify eeprom setting for MIPI camera ...................................................................... mb/google/dedede/var/storo: Modify eeprom setting for MIPI camera Solve NVM not working by modifying nvm_size from 0x0400 to 0x2000 and address_width from 0x08 to 0x10 BUG=b:177393430 TEST=1.cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin 2.hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log 3.cat ov8856_eeprom_dump.log Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/52048/1 diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index ddf1952..14eed3d 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -195,10 +195,10 @@ register "chip_name" = ""GT24C08"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "nvm_size" = "0x0400" + register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" - register "nvm_width" = "0x08" + register "nvm_width" = "0x10" register "nvm_compat" = ""atmel,24c08"" device i2c 50 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/52048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 Gerrit-Change-Number: 52048 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Subrata Banik (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/82eb79fc_ba1313d8 PS5, Line 204: #if (GFXVT_BASE_ADDRESS == 0) : #error "Error: GFXVT_BASE_ADDRESS should be non-zero for enabling VT-d!" : #endif > @Tim, the reason, i have asked is to avoid additional debug time, if you have Vtd for IGD enable and […] @Meera, you can add this check at stating of the file, no need to do inside exact code if you want -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 02:06:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Subrata Banik (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/b1a80270_8f9a61bd PS5, Line 204: #if (GFXVT_BASE_ADDRESS == 0) : #error "Error: GFXVT_BASE_ADDRESS should be non-zero for enabling VT-d!" : #endif > I think it's OK to have these as runtime checks, for example: […] @Tim, the reason, i have asked is to avoid additional debug time, if you have Vtd for IGD enable and base is zero, it cause hang. Atleast in this static method we save debug time and failure ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 02:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add initiatal for HMAT
by build bot (Jenkins) (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Lance Zhao. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52047 ) Change subject: src/acpi: Add initiatal for HMAT ...................................................................... Patch Set 1: (1 comment) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/52047/comment/fc9a1f5d_a738508c PS1, Line 250: /* Followed by latency / bandwith values */ 'bandwith' may be misspelled - perhaps 'bandwidth'? -- To view, visit https://review.coreboot.org/c/coreboot/+/52047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Gerrit-Change-Number: 52047 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Comment-Date: Fri, 02 Apr 2021 01:42:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add initiatal for HMAT
by Jonathan Zhang (Code Review) 02 Apr '21

02 Apr '21

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52047 ) Change subject: src/acpi: Add initiatal for HMAT ...................................................................... src/acpi: Add initiatal for HMAT Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 116 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52047/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index b350bc3..afae854 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -539,6 +539,48 @@ header->checksum = acpi_checksum((void *)srat, header->length); } +int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory) +{ + memset((void *)mpda, 0, sizeof(acpi_hmat_mpda_t)); + + mpda->type = 0; /* Memory Proximity Domain Attributes structure */ + mpda->length = sizeof(acpi_hmat_mpda_t); + /* Proximity Domain for Attached Initiator field is valid */ + mpda->flags = (1 << 0); + mpda->proximity_domain_initiator = initiator; + mpda->proximity_domain_memory = memory; + + return mpda->length; +} + +void acpi_create_hmat(acpi_hmat_t *hmat, + unsigned long (*acpi_fill_hmat)(unsigned long current)) +{ + acpi_header_t *header = &(hmat->header); + unsigned long current = (unsigned long)hmat + sizeof(acpi_hmat_t); + + memset((void *)hmat, 0, sizeof(acpi_hmat_t)); + + if (!header) + return; + + /* Fill out header fields. */ + memcpy(header->signature, "HMAT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->asl_compiler_revision = asl_revision; + header->length = sizeof(acpi_hmat_t); + header->revision = get_acpi_table_revision(HMAT); + + current = acpi_fill_hmat(current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)hmat; + header->checksum = acpi_checksum((void *)hmat, header->length); +} + void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)) { @@ -1736,6 +1778,8 @@ return 2; case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ + case HMAT: /* ACPI 6.4: 2 */ + return 2; case DMAR: return 1; case SLIT: /* ACPI 2.0 upto 6.3: 1 */ diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 932fb6f..37ac493 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -71,8 +71,8 @@ enum acpi_tables { /* Tables defined by ACPI and used by coreboot */ - BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG, - RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, + BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT, + MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -208,6 +208,66 @@ u8 reserved[4]; } __packed acpi_mcfg_mmconfig_t; +/* + * HMAT (Heterogeneous Memory Attribute Table) + * ACPI spec 6.4 section 5.2.27 + */ +typedef struct acpi_hmat { + acpi_header_t header; + u32 resv; + /* Followed by HMAT table structure[n] */ +} __packed acpi_hmat_t; + +/* HMAT: Memory Proximity Domain Attributes structure */ +typedef struct acpi_hmat_mpda { + u16 type; /* Type (0) */ + u16 resv; + u32 length; /* Length in bytes (40) */ + u16 flags; + u16 resv1; + u32 proximity_domain_initiator; + u32 proximity_domain_memory; + u32 resv2; + u64 resv3; + u64 resv4; +} __packed acpi_hmat_mpda_t; + +/* HMAT: System Locality Latency and Bandwidth Information structure */ +typedef struct acpi_hmat_sllbi { + u16 type; /* Type (1) */ + u16 resv; + u32 length; /* Length in bytes */ + u8 flags; + u8 data_type; + u8 min_transfer_size; + u8 resv1; + u32 num_initiator_domains; + u32 num_target_domains; + u32 resv2; + u64 entry_base_unit; + /* Followed by initiator proximity domain list */ + /* Followed by target proximity domain list */ + /* Followed by latency / bandwith values */ +} __packed acpi_hmat_sllbi_t; + +/* HMAT: Memory Side Cache Information structure */ +typedef struct acpi_hmat_msci { + u16 type; /* Type (2) */ + u16 resv; + u32 length; /* Length in bytes */ + u32 domain; /* Proximity domain for the memory */ + u32 resv1; + u64 cache_size; + u32 cache_attributes; + u16 resv2; + /* + * Number of SMBIOS handlers that contribute to the + * memory side cache physical devices + */ + u16 num_handlers; + /* Followed by SMBIOS handlers*/ +} __packed acpi_hmat_msci_t; + /* SRAT (System Resource Affinity Table) */ typedef struct acpi_srat { acpi_header_t header; @@ -1012,6 +1072,16 @@ void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +/* + * Create a Memory Proximity Domain Attributes Structure for HMAT, + * given proximity domain for the attached initiaor, and + * proximimity domain for the memory. + */ +int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory); +/* Create Heterogenous Memory Attribute Table */ +void acpi_create_hmat(acpi_hmat_t *hmat, + unsigned long (*acpi_fill_hmat)(unsigned long current)); + void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(const struct device *device, -- To view, visit https://review.coreboot.org/c/coreboot/+/52047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Gerrit-Change-Number: 52047 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Add Bluetooth configuration
by Raul Rangel (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Martin Roth, Mathew King, Bhanu Prakash Maiya, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51963 ) Change subject: mb/google/guybrush: Add Bluetooth configuration ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51963/comment/f9798fd7_47bf9b04 PS4, Line 15: Change Signed-Off -- To view, visit https://review.coreboot.org/c/coreboot/+/51963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734 Gerrit-Change-Number: 51963 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 01:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Wenbin Mei (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Wenbin Mei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 5: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51966/comment/ed8ffa59_97aaf8c2 PS2, Line 7: mmc: Add MTK mmc driver support > You are also implementing (and enabling) early init. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/51966/comment/3e8f0cfa_2fc9eebd PS3, Line 10: > 1. Did you write the driver from scratch? […] Done File src/mainboard/google/asurada/mainboard.c: https://review.coreboot.org/c/coreboot/+/51966/comment/2c76040a_bb2e9068 PS1, Line 233: struct msdc_ctrlr msdc_host; > Where? I only see it in mtk_mmc_early_init? […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/96cebf11_0bbfac52 PS1, Line 243: (void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE > this is the only place making it board-specific right? […] Done https://review.coreboot.org/c/coreboot/+/51966/comment/e6a638c3_1b9ea72d PS1, Line 247: 400*1000 > P. […] Yes, 400KHz is init clock, and all eMMCs will support it. File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/0216f304_e393adaf PS2, Line 70: udelay(1); > Sleep before read32(addr) to avoid 2 consecutive read ops (one in line #63 and the other from the fi […] Ack https://review.coreboot.org/c/coreboot/+/51966/comment/8b1d0a95_19267dac PS2, Line 72: MSDC_NOT_READY > "-MSDC_NOT_READY" is returned in msdc_poll_timeout(). Please be consistent. Done https://review.coreboot.org/c/coreboot/+/51966/comment/05491afe_6b672ba1 PS2, Line 349: host > Just "ctrlr" We need "msdc_ctrlr *" pointer as first parameter for the "msdc_start_command" function, so it should be host. https://review.coreboot.org/c/coreboot/+/51966/comment/c45f6871_07e9d94f PS2, Line 385: clrsetbits_le32 > Just clrsetbits? Please double check. Yes -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 5 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 01:09:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2021