coreboot-gerrit April 2021

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Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Karthik Ramasubramanian (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Martin Roth, Marshall Dawson, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51924 ) Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/pm/pmlib.c: https://review.coreboot.org/c/coreboot/+/51924/comment/8ee53248_ea33d07f PS2, Line 21: get_option > I can defer this i.e. defer using option table until we define the cmos_layout.bin. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 16:18:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Set Power state after power failure
by Karthik Ramasubramanian (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52049 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Set Power state after power failure ...................................................................... soc/amd/cezanne: Set Power state after power failure Configure the power state to return to when the power is re-applied after power failure. BUG=b:183739671 TEST=Build and Boot to OS in Majolica and Guybrush. By default when the power fails the device remains off even after power is re-applied. When the POWER_ON_AFTER_POWER_FAILURE is enabled, the device powers on as soon as the power is re-applied. Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/early_fch.c 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/52049/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Gerrit-Change-Number: 52049 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Handle power resume after power failure
by Karthik Ramasubramanian (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Martin Roth, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51924 to look at the new patch set (#3). Change subject: soc/amd/common: Handle power resume after power failure ...................................................................... soc/amd/common: Handle power resume after power failure Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/soc/amd/common/block/include/amdblocks/pmlib.h A src/soc/amd/common/block/pm/Kconfig A src/soc/amd/common/block/pm/Makefile.inc A src/soc/amd/common/block/pm/pmlib.c 4 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/51924/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Gerrit-Change-Number: 51924 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Add Elan Touchpad configuration
by Karthik Ramasubramanian (Code Review) 03 Apr '21

03 Apr '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51962 ) Change subject: mb/google/guybrush: Add Elan Touchpad configuration ...................................................................... mb/google/guybrush: Add Elan Touchpad configuration Enable Touchpad by configuring the enable GPIO to logic high. Add touchpad configuration for ELAN touchpad. BUG=b:182207444 TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events are detected using evtest. Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962 Reviewed-by: Mathew King <mathewk(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb 2 files changed, 11 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index e386658..ba392b4 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -22,7 +22,7 @@ /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, LOW), /* EN_PP3300_TCHPAD */ - PAD_GPO(GPIO_7, LOW), + PAD_GPO(GPIO_7, HIGH), /* EN_PWR_WWAN_X */ PAD_GPO(GPIO_8, LOW), /* SOC_TCHPAD_INT_ODL */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 286ba28..5f9b037 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -61,4 +61,14 @@ .early_init = true, }" + device ref i2c_0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + end # I2C0 end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/51962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64 Gerrit-Change-Number: 51962 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/ti/am335x/mmc.c: Fix memset length argument
by Nico Huber (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Sam Lewis, Angel Pons, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52054 ) Change subject: soc/ti/am335x/mmc.c: Fix memset length argument ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Gerrit-Change-Number: 52054 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Attention: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 02 Apr 2021 16:13:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/google/brya: Disable touchpad as S3 wake source
by Tim Wawrzynczak (Code Review) 03 Apr '21

03 Apr '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51831 ) Change subject: mainboard/google/brya: Disable touchpad as S3 wake source ...................................................................... mainboard/google/brya: Disable touchpad as S3 wake source This change disables touchpad interrupt, as it sends spurious wake signal via GPP_F14 and immediately wakes the system from S3. It happens because touchpad's power is gated by deassertion of PLTRST#. The behaviour for S0ix is unchanged. BUG=183738135 TEST=manually Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51831 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 9ff7720..6482b9c 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -236,7 +236,7 @@ /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9 Gerrit-Change-Number: 51831 Gerrit-PatchSet: 5 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mainboard/google/brya: Enable tight timestamp
by Tim Wawrzynczak (Code Review) 03 Apr '21

03 Apr '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51830 ) Change subject: mainboard/google/brya: Enable tight timestamp ...................................................................... mainboard/google/brya: Enable tight timestamp This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for CREC device BUG=none TEST=manual test Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h index fba653b..a4b8829 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -64,4 +64,6 @@ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ + #endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 578fac9..0de7ffd 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -16,5 +16,7 @@ #define GPIO_EC_IN_RW GPP_F18 /* Used to gate SoC's SLP_S0# signal */ #define GPIO_SLP_S0_GATE GPP_F9 +/* GPIO IRQ for tight timestamps / wake support */ +#define EC_SYNC_IRQ GPP_F17_IRQ #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56 Gerrit-Change-Number: 51830 Gerrit-PatchSet: 4 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP
by Tim Wawrzynczak (Code Review) 03 Apr '21

03 Apr '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51829 ) Change subject: mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP ...................................................................... mb/google/brya: change reset signal for GPP_F17 from PLTRST to DEEP PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured to reset state on PLT reset assertion. This change reconfigures the pad using DEEP instead of PLTRST to retain pad configuration across S3. BUG=b:178545523 TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake source is GPP_F17 Signed-off-by: Boris Mittelberg <bmbm(a)google.com> Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index a777f79..9ff7720 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -242,7 +242,7 @@ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17 Gerrit-Change-Number: 51829 Gerrit-PatchSet: 4 Gerrit-Owner: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/ti/am335x/mmc.c: Fix memset length argument
by Angel Pons (Code Review) 03 Apr '21

03 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52054 ) Change subject: soc/ti/am335x/mmc.c: Fix memset length argument ...................................................................... soc/ti/am335x/mmc.c: Fix memset length argument The sizeof() operator was being applied to a pointer-to-struct type. Correct this, so that the entire struct space gets cleared. Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Found-by: Coverity CID 1451732 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/ti/am335x/mmc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/52054/1 diff --git a/src/soc/ti/am335x/mmc.c b/src/soc/ti/am335x/mmc.c index 395cf4f..b7b4f97 100644 --- a/src/soc/ti/am335x/mmc.c +++ b/src/soc/ti/am335x/mmc.c @@ -260,7 +260,7 @@ int err = 0; struct sd_mmc_ctrlr *mmc_ctrlr = &mmc_host->sd_mmc_ctrlr; - memset(mmc_ctrlr, 0, sizeof(mmc_ctrlr)); + memset(mmc_ctrlr, 0, sizeof(*mmc_ctrlr)); err = am335x_mmc_init(mmc_host->reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/52054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Gerrit-Change-Number: 52054 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Subrata Banik (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/c63a0df9_04d141d0 PS5, Line 204: #if (GFXVT_BASE_ADDRESS == 0) : #error "Error: GFXVT_BASE_ADDRESS should be non-zero for enabling VT-d!" : #endif > Sure, so if you check that the user wants VT-d enabled (by checking that `InternalGfx == 1`), and yo […] perfect Tim. @Meera, please modify the code accordingly -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 16:06:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2021