coreboot-gerrit April 2021

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Change in coreboot[master]: util/kconfig_lint: Turn handle_expressions() into a parser
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Martin Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52067 ) Change subject: util/kconfig_lint: Turn handle_expressions() into a parser ...................................................................... Patch Set 1: (1 comment) File util/lint/kconfig_lint: https://review.coreboot.org/c/coreboot/+/52067/comment/287b160b_544c5eed PS1, Line 962: if ( $symbol =~ /^-?(?:0x)?\p{XDigit}+$/ ) { # hex values This actually includes int values. -- To view, visit https://review.coreboot.org/c/coreboot/+/52067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc1be79adc07792f0721f0dc08b50422b6da88a9 Gerrit-Change-Number: 52067 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 21:10:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Move early GPIO config earlier
by Furquan Shaikh (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52062 ) Change subject: mb/google/brya: Move early GPIO config earlier ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3 Gerrit-Change-Number: 52062 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 02 Apr 2021 21:03:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52072/comment/512e8fd8_c5585549 PS1, Line 10: Well we know one reason: I increases available DRAM in 32-bit space. If that's a good reason, I don't know. But we should at least mention it (and maybe add that it was fragile / not bricking is better?). -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 21:03:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52070/comment/49f8a730_dbb00253 PS1, Line 9: There's no good reason to use values smaller than 2 GiB here. Well we know one reason: I increases available DRAM in 32-bit space. If that's a good reason, I don't know. But we should at least mention it (and maybe add that it was fragile / not bricking is better?). -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 21:01:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] Rename do_printk() --> printk()
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Jason Glenesk, Nico Huber, Raul Rangel, Marshall Dawson, Kyösti Mälkki, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51887 ) Change subject: [RFC] Rename do_printk() --> printk() ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Gerrit-Change-Number: 51887 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 02 Apr 2021 21:00:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sandybridge boards: Drop default `pci_mmio_size`
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tristan Corrick, Angel Pons, Arthur Heymans, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52071 ) Change subject: sandybridge boards: Drop default `pci_mmio_size` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Gerrit-Change-Number: 52071 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 20:58:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... nb/intel/sandybridge: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/stout/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_common.c 8 files changed, 3 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52072/1 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 5461b15..73dce98 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -33,8 +33,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 18ed380..2627fae 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0x0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b4d3800..5f1ea6b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21f9 inherit diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index de91bba..e0557ca 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0f3ee5c..6cda62b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -31,8 +31,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on ioapic_irq 4 INTA 0x10 ioapic_irq 4 INTB 0x11 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 20c994e..6f49cfe 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 824af3e..99d9763 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -43,11 +43,6 @@ struct i915_gpu_controller_info gfx; - /* - * Maximum PCI MMIO size in MiB. - */ - u16 pci_mmio_size; - /* Data for RAM init */ /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d6a8aa5..7637f1f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -338,24 +338,6 @@ } } -#define DEFAULT_PCI_MMIO_SIZE 2048 - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} - /* * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. * The ME/PCU/.. has the ability to change this. @@ -382,6 +364,8 @@ return !(reg32 & (1 << 25)); } +#define DEFAULT_PCI_MMIO_SIZE 2048 + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; @@ -389,7 +373,7 @@ size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; - mmiosize = get_mmio_size(); + mmiosize = DEFAULT_PCI_MMIO_SIZE; ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sandybridge boards: Drop default `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Tristan Corrick, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52071 ) Change subject: sandybridge boards: Drop default `pci_mmio_size` ...................................................................... sandybridge boards: Drop default `pci_mmio_size` 2 GiB is the default already. Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/asus/p8z77-v_lx2/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 16 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52071/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 5050758..ee192cf 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 7b90149..22b474d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index eddca81..73671ee 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 969169c..60e54ae 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 0fc6dc1..40f8e6d 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1043 0x84ca inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 118a58e..9dc6a7c 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 0c24a9d..d753411 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1458 0x5000 inherit device pci 00.0 on # Host bridge diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index d0ec09c..479d813 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index fbff203..db902be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 61535df..f1ec5e7 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index ffd1d24..441abf2b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4b956757..6b7c6a2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index d9ececa..925bfb9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21fb inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 296be73..48d5791 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 7adc0f5..23744e1 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21f6 inherit diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 3f1934d..de0c9a2 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21db inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/52071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Gerrit-Change-Number: 52071 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/raminit.c 5 files changed, 1 insertion(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52070/1 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index af770dc..5f167df 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543d..e142a1c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b57b3fe..d5f96cb 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bc..ab589ea 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073dda..34e5657 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096) -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/zork/vilboz: Fix audio test failure on LTE SKU
by Furquan Shaikh (Code Review) 02 Apr '21

02 Apr '21

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51792 ) Change subject: mb/google/zork/vilboz: Fix audio test failure on LTE SKU ...................................................................... mb/google/zork/vilboz: Fix audio test failure on LTE SKU Use board id to switch acp_i2s_use_external_48mhz_osc enable. BUG=b:181720406 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/zork/variants/vilboz/variant.c 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve EricR Lai: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index 747e893..5006b92 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -40,6 +40,9 @@ struct soc_amd_picasso_config *soc_cfg; soc_cfg = config_of_soc(); + if (board_id() <= 2 || board_id() == BOARD_ID_UNKNOWN) + return; + /* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */ if (variant_has_wwan()) { soc_cfg->acp_i2s_use_external_48mhz_osc = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/51792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901 Gerrit-Change-Number: 51792 Gerrit-PatchSet: 10 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021