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Change subject: nb/intel/sandybridge: Drop `pci_mmio_size`
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Patch Set 1: Code-Review+2
(1 comment)
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https://review.coreboot.org/c/coreboot/+/52072/comment/512e8fd8_c5585549
PS1, Line 10:
Well we know one reason: I increases available DRAM in 32-bit space.
If that's a good reason, I don't know. But we should at least mention
it (and maybe add that it was fragile / not bricking is better?).
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Change subject: nb/intel/ironlake: Drop `pci_mmio_size`
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52070/comment/49f8a730_dbb00253
PS1, Line 9: There's no good reason to use values smaller than 2 GiB here.
Well we know one reason: I increases available DRAM in 32-bit space.
If that's a good reason, I don't know. But we should at least mention
it (and maybe add that it was fragile / not bricking is better?).
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Change subject: soc/amd/common/espi: Reset eSPI registers to known state
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Patch Set 5: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52058/comment/42dd70c6_461cf312
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
:
: On Cezanne, the PSP modifies these registers such that the eSPI
> The PSP writes port 80s to signal where it in the boot processes. i.e. […]
Ack.
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