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Change in coreboot[master]: cbfs: Add file data hashing for CONFIG_CBFS_VERIFICATION
by Julius Werner (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Furquan Shaikh, Aaron Durbin. Hello Furquan Shaikh, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52084 to review the following change. Change subject: cbfs: Add file data hashing for CONFIG_CBFS_VERIFICATION ...................................................................... cbfs: Add file data hashing for CONFIG_CBFS_VERIFICATION This patch adds file data hashing for CONFIG_CBFS_VERIFICATION. With this, all CBFS accesses using the new CBFS APIs (cbfs_load/_map/_alloc and variants) will be fully verified when verification is enabled. (Note that some use of legacy APIs remains and thus the CBFS_VERIFICATION feature is not fully finished.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ic9fff279f69cf3b7c38a0dc2ff3c970eaa756aa8 --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h M src/lib/cbfs.c 3 files changed, 74 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/52084/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 91f81e0..16bab7c 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -190,3 +190,26 @@ return NULL; } + +const struct vb2_hash *cbfs_file_hash(const union cbfs_mdata *mdata) +{ + /* Hashes are variable-length attributes, so need to manually check the length. */ + const struct cbfs_file_attr_hash *attr = + cbfs_find_attr(mdata, CBFS_FILE_ATTR_TAG_HASH, 0); + if (!attr) + return NULL; /* no hash */ + const size_t asize = be32toh(attr->len); + + const struct vb2_hash *hash = &attr->hash; + const size_t hsize = vb2_digest_size(hash->algo); + if (!hsize) { + ERROR("Hash algo %u for '%s' unsupported.\n", hash->algo, mdata->h.filename); + return NULL; + } + if (hsize != asize - offsetof(struct cbfs_file_attr_hash, hash.raw)) { + ERROR("Hash attribute size for '%s' (%zu) incorrect for algo %u.\n", + mdata->h.filename, asize, hash->algo); + return NULL; + } + return hash; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h index df13427..ed5c378 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_mdata.h @@ -24,4 +24,7 @@ else caller is responsible for checking the |len| field to avoid reading out-of-bounds. */ const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check); +/* Returns pointer to CBFS file hash structure in metadata attributes, or NULL if invalid. */ +const struct vb2_hash *cbfs_file_hash(const union cbfs_mdata *mdata); + #endif /* _COMMONLIB_BSD_CBFS_MDATA_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9135b2f..23e8f41 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -186,11 +186,27 @@ return true; } -static size_t cbfs_load_and_decompress(const struct region_device *rdev, - void *buffer, size_t buffer_size, uint32_t compression) +static inline bool cbfs_file_hash_mismatch(const void *buffer, size_t size, + const struct vb2_hash *file_hash) +{ + /* Avoid linking hash functions when verification is disabled. */ + if (!CONFIG(CBFS_VERIFICATION)) + return false; + + /* If there is no file hash, always count that as a mismatch. */ + if (file_hash && vb2_hash_verify(buffer, size, file_hash) == VB2_SUCCESS) + return false; + + printk(BIOS_CRIT, "CBFS file hash mismatch!\n"); + return true; +} + +static size_t cbfs_load_and_decompress(const struct region_device *rdev, void *buffer, + size_t buffer_size, uint32_t compression, + const struct vb2_hash *file_hash) { size_t in_size = region_device_sz(rdev); - size_t out_size; + size_t out_size = 0; void *map; DEBUG("Decompressing %zu bytes to %p with algo %d\n", in_size, buffer, compression); @@ -201,6 +217,8 @@ return 0; if (rdev_readat(rdev, buffer, 0, in_size) != in_size) return 0; + if (cbfs_file_hash_mismatch(buffer, in_size, file_hash)) + return 0; return in_size; case CBFS_COMPRESS_LZ4: @@ -213,9 +231,11 @@ if (map == NULL) return 0; - timestamp_add_now(TS_START_ULZ4F); - out_size = ulz4fn(map, in_size, buffer, buffer_size); - timestamp_add_now(TS_END_ULZ4F); + if (!cbfs_file_hash_mismatch(map, in_size, file_hash)) { + timestamp_add_now(TS_START_ULZ4F); + out_size = ulz4fn(map, in_size, buffer, buffer_size); + timestamp_add_now(TS_END_ULZ4F); + } rdev_munmap(rdev, map); @@ -228,10 +248,12 @@ if (map == NULL) return 0; - /* Note: timestamp not useful for memory-mapped media (x86) */ - timestamp_add_now(TS_START_ULZMA); - out_size = ulzman(map, in_size, buffer, buffer_size); - timestamp_add_now(TS_END_ULZMA); + if (!cbfs_file_hash_mismatch(map, in_size, file_hash)) { + /* Note: timestamp not useful for memory-mapped media (x86) */ + timestamp_add_now(TS_START_ULZMA); + out_size = ulzman(map, in_size, buffer, buffer_size); + timestamp_add_now(TS_END_ULZMA); + } rdev_munmap(rdev, map); @@ -318,11 +340,18 @@ if (size_out) *size_out = size; + const struct vb2_hash *file_hash = NULL; + if (CONFIG(CBFS_VERIFICATION)) + file_hash = cbfs_file_hash(&mdata); + /* allocator == NULL means do a cbfs_map() */ if (allocator) { loc = allocator(arg, size, &mdata); } else if (compression == CBFS_COMPRESS_NONE) { - return rdev_mmap_full(&rdev); + void *mapping = rdev_mmap_full(&rdev); + if (!mapping || cbfs_file_hash_mismatch(mapping, size, file_hash)) + return NULL; + return mapping; } else if (!CBFS_CACHE_AVAILABLE) { ERROR("Cannot map compressed file %s on x86\n", mdata.h.filename); return NULL; @@ -335,7 +364,7 @@ return NULL; } - size = cbfs_load_and_decompress(&rdev, loc, size, compression); + size = cbfs_load_and_decompress(&rdev, loc, size, compression, file_hash); if (!size) return NULL; @@ -384,12 +413,18 @@ prog_set_entry(pstage, prog_start(pstage) + be32toh(sattr->entry_offset), NULL); + const struct vb2_hash *file_hash = NULL; + if (CONFIG(CBFS_VERIFICATION)) + file_hash = cbfs_file_hash(&mdata); + /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) && !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) { void *mapping = rdev_mmap_full(&rdev); rdev_munmap(&rdev, mapping); + if (cbfs_file_hash_mismatch(mapping, region_device_sz(&rdev), file_hash)) + return CB_CBFS_HASH_MISMATCH; if (mapping == prog_start(pstage)) return CB_SUCCESS; } @@ -405,7 +440,7 @@ } size_t fsize = cbfs_load_and_decompress(&rdev, prog_start(pstage), prog_size(pstage), - compression); + compression, file_hash); if (!fsize) return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/52084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9fff279f69cf3b7c38a0dc2ff3c970eaa756aa8 Gerrit-Change-Number: 52084 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Simplify cbfs_load_and_decompress() and stop exporting it
by Julius Werner (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Furquan Shaikh, Aaron Durbin. Hello Furquan Shaikh, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52083 to review the following change. Change subject: cbfs: Simplify cbfs_load_and_decompress() and stop exporting it ...................................................................... cbfs: Simplify cbfs_load_and_decompress() and stop exporting it With the last external user to cbfs_load_and_decompress() gone, we can stop exporting this function to the rest of coreboot and make it local to cbfs.c. Also remove a couple of arguments that no longer really make a difference and fold the stage-specific code for in-place LZ4 decompression into cbfs_prog_stage_load(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4b459650a28e020c4342a66090f55264fbd26363 --- M src/include/cbfs.h M src/lib/cbfs.c 2 files changed, 21 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/52083/1 diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 37bac30..9ed5233 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -165,13 +165,6 @@ /* Return mapping of option ROM with revision number. Returns NULL on error. */ void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev); -/* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes large |buffer|, - decompressing it according to |compression| in the process. Returns the decompressed file - size, or 0 on error. LZMA files will be mapped for decompression. LZ4 files will be - decompressed in-place with the buffer size requirements outlined in compression.h. */ -size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, - size_t in_size, void *buffer, size_t buffer_size, uint32_t compression); - /********************************************************************************************** * INTERNAL HELPERS FOR INLINES, DO NOT USE. * diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 65bb721..9135b2f 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -186,19 +186,20 @@ return true; } -size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, size_t in_size, - void *buffer, size_t buffer_size, uint32_t compression) +static size_t cbfs_load_and_decompress(const struct region_device *rdev, + void *buffer, size_t buffer_size, uint32_t compression) { + size_t in_size = region_device_sz(rdev); size_t out_size; void *map; - DEBUG("Decompressing %zu bytes to %p with algo %d\n", buffer_size, buffer, compression); + DEBUG("Decompressing %zu bytes to %p with algo %d\n", in_size, buffer, compression); switch (compression) { case CBFS_COMPRESS_NONE: if (buffer_size < in_size) return 0; - if (rdev_readat(rdev, buffer, offset, in_size) != in_size) + if (rdev_readat(rdev, buffer, 0, in_size) != in_size) return 0; return in_size; @@ -206,9 +207,9 @@ if (!cbfs_lz4_enabled()) return 0; - /* cbfs_stage_load_and_decompress() takes care of in-place LZ4 decompression by + /* cbfs_prog_stage_load() takes care of in-place LZ4 decompression by setting up the rdev to be in memory. */ - map = rdev_mmap(rdev, offset, in_size); + map = rdev_mmap_full(rdev); if (map == NULL) return 0; @@ -223,7 +224,7 @@ case CBFS_COMPRESS_LZMA: if (!cbfs_lzma_enabled()) return 0; - map = rdev_mmap(rdev, offset, in_size); + map = rdev_mmap_full(rdev); if (map == NULL) return 0; @@ -241,33 +242,6 @@ } } -static size_t cbfs_stage_load_and_decompress(const struct region_device *rdev, size_t offset, - size_t in_size, void *buffer, size_t buffer_size, uint32_t compression) -{ - struct region_device rdev_src; - - if (compression == CBFS_COMPRESS_LZ4) { - if (!cbfs_lz4_enabled()) - return 0; - /* Load the compressed image to the end of the available memory area for - in-place decompression. It is the responsibility of the caller to ensure that - buffer_size is large enough (see compression.h, guaranteed by cbfstool for - stages). */ - void *compr_start = buffer + buffer_size - in_size; - if (rdev_readat(rdev, compr_start, offset, in_size) != in_size) - return 0; - /* Create a region device backed by memory. */ - rdev_chain(&rdev_src, &addrspace_32bit.rdev, (uintptr_t)compr_start, in_size); - - return cbfs_load_and_decompress(&rdev_src, 0, in_size, buffer, buffer_size, - compression); - } - - /* All other algorithms can use the generic implementation. */ - return cbfs_load_and_decompress(rdev, offset, in_size, buffer, buffer_size, - compression); -} - static inline int tohex4(unsigned int c) { return (c <= 9) ? (c + '0') : (c - 10 + 'a'); @@ -361,8 +335,7 @@ return NULL; } - size = cbfs_load_and_decompress(&rdev, 0, region_device_sz(&rdev), - loc, size, compression); + size = cbfs_load_and_decompress(&rdev, loc, size, compression); if (!size) return NULL; @@ -421,8 +394,18 @@ return CB_SUCCESS; } - size_t fsize = cbfs_stage_load_and_decompress(&rdev, 0, region_device_sz(&rdev), - prog_start(pstage), prog_size(pstage), compression); + /* LZ4 stages can be decompressed in-place to save mapping scratch space. Load the + compressed data to the end of the buffer and point &rdev to that memory location. */ + if (cbfs_lz4_enabled() && compression == CBFS_COMPRESS_LZ4) { + size_t in_size = region_device_sz(&rdev); + void *compr_start = prog_start(pstage) + prog_size(pstage) - in_size; + if (rdev_readat(&rdev, compr_start, 0, in_size) != in_size) + return CB_ERR; + rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)compr_start, in_size); + } + + size_t fsize = cbfs_load_and_decompress(&rdev, prog_start(pstage), prog_size(pstage), + compression); if (!fsize) return CB_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/52083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b459650a28e020c4342a66090f55264fbd26363 Gerrit-Change-Number: 52083 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: fsp2_0: Replace fspld->get_destination() callback with CBFS allocator
by Julius Werner (Code Review) 03 Apr '21

03 Apr '21

Attention is currently required from: Furquan Shaikh, Andrey Petrov, Patrick Rudolph, Aaron Durbin. Hello Furquan Shaikh, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52082 to review the following change. Change subject: fsp2_0: Replace fspld->get_destination() callback with CBFS allocator ...................................................................... fsp2_0: Replace fspld->get_destination() callback with CBFS allocator The Intel FSP 2.0 driver contains a custom construct that basically serves the same purpose as the new CBFS allocator concept: a callback function to customize placement of a loaded CBFS file whose size is initially unknown. This patch removes the existing implementation and replaces it with a CBFS allocator. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668 --- M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/util.c 4 files changed, 27 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/52082/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 253b74a..6583b64 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -4,6 +4,7 @@ #define _FSP2_0_UTIL_H_ #include <boot/coreboot_tables.h> +#include <cbfs.h> #include <commonlib/region.h> #include <arch/cpu.h> #include <fsp/api.h> @@ -111,11 +112,8 @@ /* fsp_prog object will have region_device initialized to final * load location in memory. */ struct prog fsp_prog; - /* Fill in destination location given final load size. Return 0 on - * success, < 0 on error. */ - int (*get_destination)(const struct fsp_load_descriptor *fspld, - void **dest, size_t final_load_size, - const struct region_device *source); + /* CBFS allocator to place loaded FSP. NULL to map flash directly. */ + cbfs_allocator_t alloc; /* Optional argument to be utilized by get_destination() callback. */ void *arg; }; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0ea5c08..bbc26bc 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -339,40 +339,20 @@ fsp_debug_after_memory_init(status); } -static int fspm_get_dest(const struct fsp_load_descriptor *fspld, void **dest, - size_t size, const struct region_device *source) +static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unused) { + const struct fsp_load_descriptor *fspld = arg; struct fspm_context *context = fspld->arg; - struct fsp_header *hdr = &context->header; struct memranges *memmap = &context->memmap; - uintptr_t fspm_begin; - uintptr_t fspm_end; - - if (CONFIG(FSP_M_XIP)) { - if (fsp_validate_component(hdr, source) != CB_SUCCESS) - return -1; - - *dest = rdev_mmap_full(source); - if ((uintptr_t)*dest != hdr->image_base) { - printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", - (void *)(uintptr_t)hdr->image_base, *dest); - return -1; - } - /* Since the component is XIP it's already in the address space. - Thus, there's no need to rdev_munmap(). */ - return 0; - } /* Non XIP FSP-M uses FSP-M address */ - fspm_begin = (uintptr_t)CONFIG_FSP_M_ADDR; - fspm_end = fspm_begin + size; + uintptr_t fspm_begin = (uintptr_t)CONFIG_FSP_M_ADDR; + uintptr_t fspm_end = fspm_begin + size; if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != CB_SUCCESS) - return -1; + return NULL; - *dest = (void *)fspm_begin; - - return 0; + return (void *)fspm_begin; } void fsp_memory_init(bool s3wake) @@ -381,12 +361,15 @@ struct fspm_context context; struct fsp_load_descriptor fspld = { .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_M_CBFS), - .get_destination = fspm_get_dest, .arg = &context, }; struct fsp_header *hdr = &context.header; struct memranges *memmap = &context.memmap; + /* For FSP-M XIP we leave alloc NULL to get a direct mapping to flash. */ + if (!CONFIG(FSP_M_XIP)) + fspld.alloc = fspm_allocator; + elog_boot_notify(s3wake); /* Build up memory map of romstage address space including CAR. */ @@ -399,6 +382,10 @@ if (fsp_load_component(&fspld, hdr) != CB_SUCCESS) die("FSPM not available or failed to load!\n"); + if (CONFIG(FSP_M_XIP) && (uintptr_t)prog_start(&fspld.fsp_prog) != hdr->image_base) + die("FSPM XIP base does not match: %p vs %p\n", + (void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog)); + timestamp_add_now(TS_BEFORE_INITRAM); do_fsp_memory_init(&context, s3wake); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index c9898f5..6326d53 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -184,22 +184,16 @@ post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT); } -static int fsps_get_dest(const struct fsp_load_descriptor *fspld, void **dest, - size_t size, const struct region_device *source) +static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused) { - *dest = cbmem_add(CBMEM_ID_REFCODE, size); - - if (*dest == NULL) - return -1; - - return 0; + return cbmem_add(CBMEM_ID_REFCODE, size); } void fsps_load(void) { struct fsp_load_descriptor fspld = { .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS), - .get_destination = fsps_get_dest, + .alloc = fsps_allocator, }; struct prog *fsps = &fspld.fsp_prog; static int load_done; diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 9831e64..33bfc11 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -139,65 +139,24 @@ return false; } -static void *fsp_get_dest_and_load(struct fsp_load_descriptor *fspld, size_t size, - const struct region_device *source_rdev, - uint32_t compression_algo) -{ - void *dest; - - if (fspld->get_destination(fspld, &dest, size, source_rdev) < 0) { - printk(BIOS_ERR, "FSP Destination not obtained.\n"); - return NULL; - } - - /* Don't load when executing in place. */ - if (fspm_xip()) - return dest; - - if (cbfs_load_and_decompress(source_rdev, 0, region_device_sz(source_rdev), - dest, size, compression_algo) != size) { - printk(BIOS_ERR, "Failed to load FSP component.\n"); - return NULL; - } - - /* Don't allow FSP-M relocation. */ - if (fspm_env()) - return dest; - - if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { - printk(BIOS_ERR, "Unable to relocate FSP component!\n"); - return NULL; - } - - return dest; -} - /* Load the FSP component described by fsp_load_descriptor from cbfs. The FSP * header object will be validated and filled in on successful load. */ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_header *hdr) { - struct cbfsf file_desc; - uint32_t compression_algo; size_t output_size; void *dest; - struct region_device source_rdev, prog_rdev; + struct region_device prog_rdev; struct prog *fsp_prog = &fspld->fsp_prog; - if (fspld->get_destination == NULL) + dest = cbfs_alloc(prog_name(fsp_prog), fspld->alloc, fspld, &output_size); + if (!dest) return CB_ERR; - if (cbfs_boot_locate(&file_desc, prog_name(fsp_prog), &fsp_prog->cbfs_type) < 0) + /* Don't allow FSP-M relocation. */ + if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) { + printk(BIOS_ERR, "Unable to relocate FSP component!\n"); return CB_ERR; - - if (cbfsf_decompression_info(&file_desc, &compression_algo, &output_size) < 0) - return CB_ERR; - - cbfs_file_data(&source_rdev, &file_desc); - - dest = fsp_get_dest_and_load(fspld, output_size, &source_rdev, compression_algo); - - if (dest == NULL) - return CB_ERR; + } prog_set_area(fsp_prog, dest, output_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/52082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668 Gerrit-Change-Number: 52082 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfs: Make `mdata` argument to cbfs_allocator_t const
by Julius Werner (Code Review) 03 Apr '21

03 Apr '21

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Change in coreboot[master]: nb/intel/i945/raminit.c: Replace `DIMM0`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52073 ) Change subject: nb/intel/i945/raminit.c: Replace `DIMM0` ...................................................................... nb/intel/i945/raminit.c: Replace `DIMM0` Use the actual value as it is more informative. Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/52073/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6b1bdb9..ce620ac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -45,7 +45,7 @@ if (sysinfo->spd_addresses) return sysinfo->spd_addresses[device]; else - return DIMM0 + device; + return 0x50 + device; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Gerrit-Change-Number: 52073 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Update CpuRatio settings
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Kaiyen Chang, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52029 ) Change subject: soc/intel/jasperlake: Update CpuRatio settings ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52029/comment/10a1a146_585840e8 PS3, Line 11: fsp_param.c nit: missing an `s`: `fsp_params.c` -- To view, visit https://review.coreboot.org/c/coreboot/+/52029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b9d5620b8e394201e82185eb28b67d6702b2d5 Gerrit-Change-Number: 52029 Gerrit-PatchSet: 3 Gerrit-Owner: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kaiyen Chang <kaiyen.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kaiyen Chang <kaiyen.chang(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 22:10:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Arthur Heymans, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52072/comment/7913a5cd_8cab612c PS1, Line 10: > Well we know one reason: I increases available DRAM in 32-bit space. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 22:08:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52072 to look at the new patch set (#2). Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... nb/intel/sandybridge: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/stout/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_common.c 8 files changed, 3 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/52072/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Nico Huber (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52070/comment/59bcf271_7801cb8f PS1, Line 9: There's no good reason to use values smaller than 2 GiB here. > Well we know one reason: I increases available DRAM in 32-bit space. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 02 Apr 2021 22:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Angel Pons (Code Review) 02 Apr '21

02 Apr '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52070 to look at the new patch set (#2). Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/raminit.c 5 files changed, 1 insertion(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/52070/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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