Hello build bot (Jenkins), Bill XIE, Nico Huber, Michał Żygowski, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48708
to look at the new patch set (#19).
Change subject: [UNTESTED] mb/supermicro/x11ssh-f: configure the BMC jumper JPB1
......................................................................
[UNTESTED] mb/supermicro/x11ssh-f: configure the BMC jumper JPB1
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value. Also, configure the pad accordingly.
Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.
Change-Id: I11c2b34c0871170e76ff6a83ffa4e45be121da3b
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48708/19
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Gerrit-Change-Number: 48708
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Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, Jingle Hsu, Arthur Heymans, Patrick Rudolph, Marc Jones, Anjaneya "Reddy" Chagam, Nico Huber, Johnny Lin, Tim Wawrzynczak, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48671
to look at the new patch set (#20).
Change subject: mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
......................................................................
mb/ocp/tiogapass: use IPMI driver functionality for "POST complete"
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/ocp/tiogapass/devicetree.cb
M src/mainboard/ocp/tiogapass/ramstage.c
2 files changed, 4 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48671/20
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Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, Jingle Hsu, Arthur Heymans, Patrick Rudolph, Marc Jones, Anjaneya "Reddy" Chagam, Nico Huber, Johnny Lin, Christian Walter, Tim Wawrzynczak, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48670
to look at the new patch set (#20).
Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value
......................................................................
mb/ocp/tiogapass: correct "POST complete" pad initial value
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48670/20
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Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, Jingle Hsu, Arthur Heymans, Patrick Rudolph, Marc Jones, Anjaneya "Reddy" Chagam, Nico Huber, Johnny Lin, Tim Wawrzynczak, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48671
to look at the new patch set (#19).
Change subject: mb/ocp/tiogapass: replace "POST complete" mb code with driver functionality
......................................................................
mb/ocp/tiogapass: replace "POST complete" mb code with driver functionality
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/ocp/tiogapass/devicetree.cb
M src/mainboard/ocp/tiogapass/ramstage.c
2 files changed, 4 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48671/19
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Hello build bot (Jenkins), Jonathan Zhang, Paul Menzel, Jingle Hsu, Arthur Heymans, Patrick Rudolph, Marc Jones, Anjaneya "Reddy" Chagam, Nico Huber, Johnny Lin, Christian Walter, Tim Wawrzynczak, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48670
to look at the new patch set (#19).
Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value
......................................................................
mb/ocp/tiogapass: correct "POST complete" pad initial value
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48670/19
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49887 )
Change subject: docs/mb/supermicro: add SUM tool for flashing with disabled ME
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File Documentation/mainboard/supermicro/flashing_on_vendorbmc.md:
https://review.coreboot.org/c/coreboot/+/49887/comment/32e2dd52_f8c951ca
PS3, Line 36: by
nit: I'd use `via`
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52092 )
Change subject: mb/ocp/tiogapass: enable SOL console via Kconfig
......................................................................
Set Ready For Review
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Change subject: mb/ocp/deltalake: enable SOL console via Kconfig
......................................................................
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Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/52089
to review the following change.
Change subject: mb/hp: Do not set EC SLPT on S5 for EliteBook laptops
......................................................................
mb/hp: Do not set EC SLPT on S5 for EliteBook laptops
This fixes https://ticket.coreboot.org/issues/304.
Tested on HP EliteBook 2560p, reboot and S3 resume work after
this change.
Change-Id: I9b3ea737f85cc4045714263657bcdaac08f3a20d
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
M src/mainboard/hp/folio_9480m/acpi/platform.asl
M src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl
2 files changed, 8 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/52089/1
diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl
index 8023ae8..d17f575 100644
--- a/src/mainboard/hp/folio_9480m/acpi/platform.asl
+++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl
@@ -10,5 +10,8 @@
Method(_PTS,1)
{
- \_SB.PCI0.LPCB.EC0.SLPT = Arg0
+ If (Arg0 != 5)
+ {
+ \_SB.PCI0.LPCB.EC0.SLPT = Arg0
+ }
}
diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl
index 8023ae8..d17f575 100644
--- a/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl
+++ b/src/mainboard/hp/snb_ivb_laptops/acpi/platform.asl
@@ -10,5 +10,8 @@
Method(_PTS,1)
{
- \_SB.PCI0.LPCB.EC0.SLPT = Arg0
+ If (Arg0 != 5)
+ {
+ \_SB.PCI0.LPCB.EC0.SLPT = Arg0
+ }
}
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