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Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS1:
> All datasheets I looked at say LPC BIOS_CNTL is 8 bits, and
eSPI and SPI BIOS_CNTL is 32 bits. I've never seen 16 bits
so far. It might not matter, though, if the LPC register
doesn't mind bigger reads/writes.
Intel......... eSPI and LPC/SPI are both 32 bits, too. Intel just didn't mention that in the datasheet. Source: refcode and Intel doc#545845.
AFAICS the fast_spi code does get used by eSPI as well bc the spi part of eSPI is compatible and since the BIOS_CONTROL register and the status bit have the same offset, it will get cleared on eSPI, too.
There are google boards with kbl, cnl and others, that could be tested. @Tim @Matt
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Change subject: mb/prodrive/hermes: Properly pack EEPROM structures
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/prodrive/hermes: Properly pack EEPROM structures
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h:
https://review.coreboot.org/c/coreboot/+/51980/comment/d48d6c10_0b4a0e96
PS3, Line 39: __packed
> not sure if there is a rule about it, but isn't __packed usually written after the closing bracked? […]
No, there isn't a rule about it. Both placements work, but I prefer to put it at the start. vc/amd/fsp/ also does the same.
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Change subject: mb/prodrive/hermes: Properly pack EEPROM structures
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h:
https://review.coreboot.org/c/coreboot/+/51980/comment/d60864d4_5cbc2e5a
PS3, Line 39: __packed
not sure if there is a rule about it, but isn't __packed usually written after the closing bracked? `} __packed;`
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Change subject: docs/mb/supermicro: add SUM tool for flashing with disabled ME
......................................................................
Patch Set 4: Code-Review+2
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Change subject: docs/mb/supermicro: add SUM tool for flashing with disabled ME
......................................................................
Patch Set 4:
(1 comment)
File Documentation/mainboard/supermicro/flashing_on_vendorbmc.md:
https://review.coreboot.org/c/coreboot/+/49887/comment/d615daab_00fe5dcf
PS3, Line 36: by
> nit: I'd use `via`
Ack
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Change subject: docs/mb/supermicro: add SUM tool for flashing with disabled ME
......................................................................
docs/mb/supermicro: add SUM tool for flashing with disabled ME
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9
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---
M Documentation/mainboard/supermicro/flashing_on_vendorbmc.md
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/49887/4
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Change subject: mb/ocp/tiogapass: correct "POST complete" pad initial value
......................................................................
Patch Set 20: Code-Review+1
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Change subject: [UNTESTED] mb/supermicro/x11ssh-tf: configure the BMC jumper JPB1
......................................................................
[UNTESTED] mb/supermicro/x11ssh-tf: configure the BMC jumper JPB1
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value.
Also disable the non-required interrupt and add a comment to the pad.
Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.
Change-Id: I3a5128007b1606576a28ddba576bd964612357f8
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48709/19
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Change subject: [UNTESTED] mb/supermicro/x11ssh-f: configure "POST complete" gpio for IPMI driver
......................................................................
[UNTESTED] mb/supermicro/x11ssh-f: configure "POST complete" gpio for IPMI driver
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver and set the pad's initial value to 0 since the signal is active-
high and shall be set by the IPMI/BMC driver.
Also add the pad to early gpio config, since it is expected to have an
external pull-up like X11SSM-F, which is wrong and would confuse the BMC.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I671d16268e09a2eb80e0154a56fa002a040ac1fb
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
3 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48710/19
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