coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52099/comment/f493702f_b339515e PS1, Line 96: default n > As it’s user-visible, could you please add a description? That’d be great. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 19:30:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52099 to look at the new patch set (#2). Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... soc/intel/skylake: Move `SataTestMode` to Kconfig This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/52099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Michael Niewöhner (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 19:18:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Paul Menzel (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Angel Pons, Michael Niewöhner, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52099/comment/20499e26_ed414905 PS1, Line 96: default n As it’s user-visible, could you please add a description? That’d be great. -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 18:05:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... soc/intel/skylake: Move `SataTestMode` to Kconfig This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/52099/1 diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 8784080..98fccc9 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -75,9 +75,6 @@ [3] = 1, }" # DevSlp not supported - - # Enable test mode for SATA margining - register "SataTestMode" = "1" end device pci 19.0 on end # UART #2 device pci 1c.0 off end # RP #1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 29f8159..6a0de2c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -91,6 +91,10 @@ bool "Enable Hyper-Threading" default y +config ENABLE_SATA_TEST_MODE + bool "Enable SATA test mode" + default n + config CPU_INTEL_NUM_FIT_ENTRIES int default 10 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 2a7c02a..6bc0922 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -314,7 +314,7 @@ * write" errors and others. Enabling this option solves these problems. */ params->SataPwrOptEnable = 1; - tconfig->SataTestMode = config->SataTestMode; + tconfig->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE); } memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 99eb8e6..e207be4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -480,9 +480,6 @@ */ u8 IslVrCmd; - /* Enable/Disable Sata test mode */ - u8 SataTestMode; - /* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: skylake mainboards: Use enum values for SaGv
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52098 ) Change subject: skylake mainboards: Use enum values for SaGv ...................................................................... skylake mainboards: Use enum values for SaGv Replace `3` with `SaGv_Enabled`, which has the same value. Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb 11 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52098/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0531fa..07b9100 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -45,7 +45,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e9d5a35..d33c9fd 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -76,7 +76,7 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 5a48c5d..3f7ce89 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d3e351a..e779ae4 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -52,7 +52,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 09bdac4..c5d8539 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 25d720e..885fcbd 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -39,7 +39,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6eb83ac..3c7930d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 39e241e..2b7debd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -45,7 +45,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 05f62e7..4ea4740 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -52,7 +52,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ac8fbc9..df571aa 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index c3a9567..2c621b6 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -55,7 +55,7 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms -- To view, visit https://review.coreboot.org/c/coreboot/+/52098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Gerrit-Change-Number: 52098 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: skylake DT/HALO mainboards: Drop `SaGv` setting
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Michael Niewöhner. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52097 ) Change subject: skylake DT/HALO mainboards: Drop `SaGv` setting ...................................................................... skylake DT/HALO mainboards: Drop `SaGv` setting SaGv is only supported on ULT/ULX hardware. Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 3 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52097/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 74e5720..0acba3a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -19,7 +19,6 @@ # FSP Configuration register "PrimaryDisplay" = "Display_PEG" - register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index d049db1..44ff902 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -20,8 +20,6 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "SaGv" = "SaGv_Enabled" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 76aec3f..1196629 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -2,7 +2,6 @@ # FSP Configuration register "SkipExtGfxScan" = "1" - register "SaGv" = "SaGv_Disabled" # SATA configuration register "SataSalpSupport" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/52097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b Gerrit-Change-Number: 52097 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Michael Niewöhner (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Aaron Durbin, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/52093/comment/3b527a40_95a9fe5b PS1, Line 77: : if (base == 0) : return; : > I thought it would be useful to know when this function is called with base=0. […] Yeah, but the message is still far away from what the code does. What about either moving it up and print sth like "LPC: skipping non-io-window 0", or printing "Skipped invalid IO window 0" below? -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 14:20:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Arthur Heymans, Michael Niewöhner, Aaron Durbin, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/52093/comment/39d2ebbe_2620d2ed PS1, Line 77: : if (base == 0) : return; : > move above printk? we never "try to open" these non-windows I thought it would be useful to know when this function is called with base=0. It's also BIOS_SPEW loglevel, so it would usually not be printed. -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 14:14:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/i945/raminit.c: Replace `DIMM0`
by Michael Niewöhner (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52073 ) Change subject: nb/intel/i945/raminit.c: Replace `DIMM0` ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/c/coreboot/+/52073/comment/5c9b86d5_ace5baff PS1, Line 48: 0x50 > There's no rule saying that SPD index 0x50 is DIMM0. […] ok, thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/52073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Gerrit-Change-Number: 52073 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 14:08:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021