coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Michael Niewöhner (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Paul Menzel, Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 11:25:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52108 ) Change subject: soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree ...................................................................... soc/intel/alderlake: Drop unused `PrmrrSize` from devicetree The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h 4 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52108/1 diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index cade987..9ad0a4f 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -50,8 +50,6 @@ register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" - register "PrmrrSize" = "0" - # Enable PCH PCIE RP 5 using CLK 2 register "pch_pcie_rp[PCH_RP(5)]" = "{ .clk_src = 2, diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 3094010..3e40691 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -36,8 +36,6 @@ register "gen3_dec" = "0x00fc0901" register "gen4_dec" = "0x000c0081" - register "PrmrrSize" = "0" - #Enable PCH PCIE RP 4 using CLK 5 register "pch_pcie_rp[PCH_RP(4)]" = "{ .clk_src = 5, diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 98f6400..dfeb32b 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -43,7 +43,6 @@ register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0" # Enable PCH PCIE RP 5 using CLK 1 register "pch_pcie_rp[PCH_RP(5)]" = "{ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 92d53a9..524a61a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -161,16 +161,6 @@ /* Enable C6 DRAM */ uint8_t enable_c6dram; - /* - * PRMRR size setting with below options - * Disable: 0x0 - * 32MB: 0x2000000 - * 64MB: 0x4000000 - * 128 MB: 0x8000000 - * 256 MB: 0x10000000 - * 512 MB: 0x20000000 - */ - uint32_t PrmrrSize; uint8_t PmTimerDisabled; /* * SerialIO device mode selection: -- To view, visit https://review.coreboot.org/c/coreboot/+/52108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Gerrit-Change-Number: 52108 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Replace open-coded buffer length calculation
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52107 ) Change subject: soc/intel: Replace open-coded buffer length calculation ...................................................................... soc/intel: Replace open-coded buffer length calculation Use `sizeof(value)` instead of manually calculating the buffer size. Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/tigerlake/chip.c 6 files changed, 12 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/52107/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index dc54845..f4d0241 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -116,11 +116,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 2c2dcdb..4307260 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -14,11 +14,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index 3917ea0..ad63481 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -105,11 +105,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 32b1830..05f42b4 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -95,11 +95,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index ea29fd8..a8e3c88 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -111,11 +111,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 1affcce..eefc408 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -116,11 +116,9 @@ const config_t *config = config_of_soc(); if (config->gpio_override_pm) - memcpy(value, config->gpio_pm, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memcpy(value, config->gpio_pm, sizeof(value)); else - memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) * - TOTAL_GPIO_COMM); + memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value)); gpio_pm_configure(value, TOTAL_GPIO_COMM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197 Gerrit-Change-Number: 52107 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Fix typo in comment
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52106 ) Change subject: soc/intel: Fix typo in comment ...................................................................... soc/intel: Fix typo in comment rotine ---> routine Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/tigerlake/chip.c 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/52106/1 diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c index 21a5801..2c2dcdb 100644 --- a/src/soc/intel/cannonlake/gpio_common.c +++ b/src/soc/intel/cannonlake/gpio_common.c @@ -5,7 +5,7 @@ /* * Routine to perform below operations: - * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register + * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register * 2. Program GPIO PM configuration based on PM mask and value */ void soc_gpio_pm_configuration(void) diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index b14edd6..3917ea0 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -98,7 +98,7 @@ } #endif -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 821a9e0..32b1830 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -88,7 +88,7 @@ } #endif -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 1051fbc..ea29fd8 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -104,7 +104,7 @@ } #endif -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 2a0d7d0..1affcce 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -109,7 +109,7 @@ } #endif -/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; -- To view, visit https://review.coreboot.org/c/coreboot/+/52106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168 Gerrit-Change-Number: 52106 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Drop unreferenced `SkipExtGfxScan`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52105 ) Change subject: soc/intel: Drop unreferenced `SkipExtGfxScan` ...................................................................... soc/intel: Drop unreferenced `SkipExtGfxScan` This option is not referenced anywhere. Drop it. Change-Id: I296d20b4a13b73260aa5343ea72bdd3c770b7656 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 6 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52105/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 164d1b9..92d53a9 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -149,7 +149,6 @@ IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, } IgdDvmt50PreAlloc; - uint8_t SkipExtGfxScan; /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a9b6c4c..5bdbdee 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -196,9 +196,6 @@ /* Heci related */ uint8_t DisableHeciRetry; - /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable; /* CPU PL2/4 Config diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index c3a7ac1..a148cf1 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -128,9 +128,6 @@ /* Enable if SD Card Power Enable Signal is Active High */ uint8_t SdCardPowerEnableActiveHigh; - /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index bef9adb..4db8a4d 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -129,9 +129,6 @@ /* Heci related */ uint8_t Heci3Enabled; - /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index c25ccbf..a1cdeeec 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -130,9 +130,6 @@ uint16_t ImonSlope; uint16_t ImonOffset; - /* Gfx related */ - uint8_t SkipExtGfxScan; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index af9b310..16260a1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -264,9 +264,6 @@ /* SMBus */ uint8_t SmbusEnable; - /* Gfx related */ - uint8_t SkipExtGfxScan; - uint8_t Device4Enable; /* HeciEnabled decides the state of Heci1 at end of boot -- To view, visit https://review.coreboot.org/c/coreboot/+/52105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296d20b4a13b73260aa5343ea72bdd3c770b7656 Gerrit-Change-Number: 52105 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Drop unreferenced `InternalGfx`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52104 ) Change subject: soc/intel/alderlake: Drop unreferenced `InternalGfx` ...................................................................... soc/intel/alderlake: Drop unreferenced `InternalGfx` This option is not referenced anywhere. Drop it. Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/alderlake/chip.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/52104/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 3bee09d..164d1b9 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -149,7 +149,6 @@ IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, } IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; /* HeciEnabled decides the state of Heci1 at end of boot -- To view, visit https://review.coreboot.org/c/coreboot/+/52104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Gerrit-Change-Number: 52104 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Drop unused `SataDevSlpRstConfig`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52103 ) Change subject: soc/intel/cannonlake: Drop unused `SataDevSlpRstConfig` ...................................................................... soc/intel/cannonlake: Drop unused `SataDevSlpRstConfig` This option is not referenced anywhere. Drop it. Change-Id: Iff3e896463575295c489032e04955bb5a7ba6355 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/chip.h 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/52103/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f84a480..a9b6c4c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -112,14 +112,6 @@ SATA_RAID, } SataMode; - /* SATA devslp pad reset configuration */ - enum { - SataDevSlpResumeReset = 1, - SataDevSlpHostDeepReset = 3, - SataDevSlpPlatformReset = 5, - SataDevSlpDswReset = 7 - } SataDevSlpRstConfig; - uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/52103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3e896463575295c489032e04955bb5a7ba6355 Gerrit-Change-Number: 52103 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Felix Singer, Jeremy Soller, Michael Niewöhner, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52102 ) Change subject: soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd` ...................................................................... soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd` This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/icelake/chip.h 4 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52102/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index fed1325..05f2a56 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -9,9 +9,6 @@ }, }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 313329a..a0b6403 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -9,9 +9,6 @@ }, }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f9f761b..f84a480 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -223,13 +223,6 @@ /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; - /* Enable VR specific mailbox command - * 00b - no VR specific cmd sent - * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent - * 10b - VR specific cmd sent for PS4 exit issue - * 11b - Reserved */ - uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index b878fd6..bef9adb 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -138,13 +138,6 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Enable VR specific mailbox command - * 00b - no VR specific cmd sent - * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent - * 10b - VR specific cmd sent for PS4 exit issue - * 11b - Reserved */ - uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/52102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Gerrit-Change-Number: 52102 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52101 ) Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option ...................................................................... soc/intel/skylake: Drop unnecessary `ignore_vtd` option It is zero for all mainboards. If one really wanted to ignore VT-d support, a user-visible Kconfig option would be a better approach. Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/protectli/vault_kbl/devicetree.cb M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 6 files changed, 3 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/52101/1 diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index abbfda4..dc73f91 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -22,9 +22,6 @@ # Disable DPTF register "dptf_enable" = "0" - # Enable VT-d - register "ignore_vtd" = "0" - # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 0d89f29..3434aac 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -460,11 +460,10 @@ unsigned long current, struct acpi_rsdp *const rsdp) { - const struct soc_intel_skylake_config *const config = config_of(dev); acpi_dmar_t *const dmar = (acpi_dmar_t *)current; /* Create DMAR table only if we have VT-d capability. */ - if (config->ignore_vtd || !soc_is_vtd_capable()) + if (!soc_is_vtd_capable()) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0ae98a9..d4d8938 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -524,7 +524,7 @@ params->PchIoApicBdfValid = 0; /* Enable VT-d and X2APIC */ - if (!config->ignore_vtd && soc_is_vtd_capable()) { + if (soc_is_vtd_capable()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 99eb8e6..1c8ca49 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -78,9 +78,6 @@ /* TCC activation offset */ uint32_t tcc_offset; - /* Whether to ignore VT-d support of the SKU */ - int ignore_vtd; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index f22fd53..8996bce 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -13,11 +13,6 @@ static void systemagent_vtd_init(void) { const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const struct soc_intel_skylake_config *config = NULL; - - config = config_of_soc(); - if (config->ignore_vtd) - return; const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 785a5e6..17dcb38 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -44,7 +44,7 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - if (!config->ignore_vtd && soc_is_vtd_capable()) { + if (soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/52101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Gerrit-Change-Number: 52101 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49470 ) Change subject: soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > ugh. […] CB:52100 hooks it up to some more platforms -- To view, visit https://review.coreboot.org/c/coreboot/+/49470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9 Gerrit-Change-Number: 49470 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Apr 2021 09:52:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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