coreboot-gerrit April 2021

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Change in coreboot[master]: Documentation: Fix formatting in BBB doc
by Sam Lewis (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Paul Menzel. Sam Lewis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50988 ) Change subject: Documentation: Fix formatting in BBB doc ...................................................................... Patch Set 2: (1 comment) File Documentation/mainboard/ti/beaglebone-black.md: https://review.coreboot.org/c/coreboot/+/50988/comment/262ebd93_d1686d15 PS1, Line 131: [U-Boot Falcon mode]: https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon > While at it, you can also add the newline to the end of the file. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea5a74789213170c514de4b14c69375eb4cf85e1 Gerrit-Change-Number: 50988 Gerrit-PatchSet: 2 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Apr 2021 01:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix formatting in BBB doc
by Sam Lewis (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Sam Lewis. Hello build bot (Jenkins), Paul Menzel, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50988 to look at the new patch set (#2). Change subject: Documentation: Fix formatting in BBB doc ...................................................................... Documentation: Fix formatting in BBB doc Fixes a few formatting errors in the Beaglebone Black documentation page, so that it renders as intended. Change-Id: Iea5a74789213170c514de4b14c69375eb4cf85e1 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M Documentation/mainboard/ti/beaglebone-black.md 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50988/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea5a74789213170c514de4b14c69375eb4cf85e1 Gerrit-Change-Number: 50988 Gerrit-PatchSet: 2 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Disable all eSPI decodes except 0x80
by Raul Rangel (Code Review) 04 Apr '21

04 Apr '21

Raul Rangel has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51927 ) Change subject: soc/amd/common: Disable all eSPI decodes except 0x80 ...................................................................... Abandoned Included in Martin's changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/51927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2e38bf888433eb9913ee64a607a236a79077a72 Gerrit-Change-Number: 51927 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN
by Raul Rangel (Code Review) 04 Apr '21

04 Apr '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52055 ) Change subject: soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN ...................................................................... soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_EN This matches the other register definitions. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 152cdd9..45fcc6f 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -337,7 +337,7 @@ #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) #define ESPI_SUB_DECODE_EN (1 << 2) -#define SLAVE0_INT_STS 0x70 +#define ESPI_SLAVE0_INT_STS 0x70 #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) #define ESPI_STATUS_FATAL_ERROR (1 << 5) @@ -418,9 +418,9 @@ /* Clear interrupt status register */ static void espi_clear_status(void) { - uint32_t status = espi_read32(SLAVE0_INT_STS); + uint32_t status = espi_read32(ESPI_SLAVE0_INT_STS); if (status) - espi_write32(SLAVE0_INT_STS, status); + espi_write32(ESPI_SLAVE0_INT_STS, status); } /* @@ -433,7 +433,7 @@ stopwatch_init_usecs_expire(&sw, ESPI_CMD_TIMEOUT_US); do { - *status = espi_read32(SLAVE0_INT_STS); + *status = espi_read32(ESPI_SLAVE0_INT_STS); if (*status) return 0; } while (!stopwatch_expired(&sw)); -- To view, visit https://review.coreboot.org/c/coreboot/+/52055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Gerrit-Change-Number: 52055 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Clear eSPI ranges before configuring eSPI
by Raul Rangel (Code Review) 04 Apr '21

04 Apr '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51749 ) Change subject: soc/amd/cezanne: Clear eSPI ranges before configuring eSPI ...................................................................... soc/amd/cezanne: Clear eSPI ranges before configuring eSPI The Cezanne PSP configures the eSPI with the assumption that it's a majolica, setting up both the serial port and the majolica EC IO decode ranges. Since guybrush is NOT a majolica, this doesn't work very well there. Clearing the decode ranges allows the guybrush platform to set the decode ranges needed for its EC. BUG=b:183524609 TEST=Set up eSPI on Guybrush Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/cezanne/early_fch.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 0c72863..acd2a7a 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -68,6 +68,7 @@ lpc_disable_spi_rom_sharing(); if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + espi_clear_decodes(); espi_setup(); espi_configure_decodes(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5 Gerrit-Change-Number: 51749 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Add func to clear eSPI IO & memory decode ranges
by Raul Rangel (Code Review) 04 Apr '21

04 Apr '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51748 ) Change subject: soc/amd/common: Add func to clear eSPI IO & memory decode ranges ...................................................................... soc/amd/common: Add func to clear eSPI IO & memory decode ranges Previously, the eSPI code would only add to existing decode ranges, and there wasn't any way to clear ranges. This clears all the ranges so the eSPI configuration can start fresh. BUG=b:183207262, b:183974365 TEST=Verify on Guybrush Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index c593e02..7ca5b05 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -107,6 +107,13 @@ void espi_configure_decodes(void); /* + * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing + * the decodes, or if something else has previously setup decode windows that conflict + * with the windows that coreboot needs. + */ +void espi_clear_decodes(void); + +/* * In cases where eSPI BAR is statically provided by SoC, use that BAR instead of reading * SPIBASE. This is required for cases where verstage runs on PSP. */ diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 0878fb7..152cdd9 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -98,6 +98,27 @@ return -1; } +void espi_clear_decodes(void) +{ + unsigned int idx; + + /* First turn off all enable bits, then zero base, range, and size registers */ + /* + * There is currently a bug where the SMU will lock up at times if the port80h enable + * bit is cleared. See b/183974365 + */ + espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + + for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { + espi_write16(ESPI_IO_RANGE_BASE(idx), 0); + espi_write8(ESPI_IO_RANGE_SIZE(idx), 0); + } + for (idx = 0; idx < ESPI_GENERIC_MMIO_WIN_COUNT; idx++) { + espi_write32(ESPI_MMIO_RANGE_BASE(idx), 0); + espi_write16(ESPI_MMIO_RANGE_SIZE(idx), 0); + } +} + /* * Returns decode enable bits for standard IO port addresses. If port address is not supported * by standard decode or if the size of window is not 1, then it returns -1. -- To view, visit https://review.coreboot.org/c/coreboot/+/51748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Gerrit-Change-Number: 51748 Gerrit-PatchSet: 9 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by Rocky Phagura (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Marc Jones, Furquan Shaikh, Duncan Laurie, Angel Pons. Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49286 ) Change subject: src/acpi: Add APEI EINJ support ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Rebase, plus 1 bug fix in acpi.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 6 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Apr 2021 21:26:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/acpi: Add APEI EINJ support
by Rocky Phagura (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Marc Jones, Furquan Shaikh, Duncan Laurie, Angel Pons. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Jonathan Zhang, Duncan Laurie, Paul Menzel, Rocky Phagura, Subrata Banik, Angel Pons, Patrick Rudolph, Lance Zhao, Marc Jones, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49286 to look at the new patch set (#6). Change subject: src/acpi: Add APEI EINJ support ...................................................................... src/acpi: Add APEI EINJ support This adds full EINJ support with trigger action tables. The actual error injection functionality is HW specific. Therefore, HW specific code should call acpi_create_einj with an address where action table resides. The default params of the action table are filled out by the common code. Control is then returned back to the caller to modify or override default parameters. If no changes are needed, caller can simply add the acpi table. At runtime, FW is responsible for filling out the action table with the proper entries. The action table memory is shared between FW and OS. This memory should be marked as reserved in E820 table. Tested on Deltalake mainboard. Boot to OS, load the EINJ driver ( modprobe EINJ) and verify EINJ memory entries are in /proc/iomem. Further tested by injecting errors via the APEI file nodes. More information on error injection is here. https://www.kernel.org/doc/Documentation/acpi/apei/einj.txt Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Signed-off-by: Rocky Phagura <rphagura(a)fb.com> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/include/acpi/acpi.h 3 files changed, 289 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/49286/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Gerrit-Change-Number: 49286 Gerrit-PatchSet: 6 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Duncan Laurie <duncan(a)iceblink.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52099 ) Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52099/comment/f493702f_b339515e PS1, Line 96: default n > As it’s user-visible, could you please add a description? That’d be great. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 19:30:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Move `SataTestMode` to Kconfig
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52099 to look at the new patch set (#2). Change subject: soc/intel/skylake: Move `SataTestMode` to Kconfig ...................................................................... soc/intel/skylake: Move `SataTestMode` to Kconfig This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/280_g2/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 4 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/52099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Gerrit-Change-Number: 52099 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021