coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Michael Niewöhner (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Aaron Durbin, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/52093/comment/e33f0f56_adc27738 PS1, Line 77: : if (base == 0) : return; : move above printk? we never "try to open" these non-windows -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 14:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Always use `CHIPSET_LOCKDOWN_COREBOOT`
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52096 ) Change subject: soc/intel/skylake: Always use `CHIPSET_LOCKDOWN_COREBOOT` ...................................................................... soc/intel/skylake: Always use `CHIPSET_LOCKDOWN_COREBOOT` FSP lockdown is not documented and could change after a FSP update, yet it is somehow the default choice if the devicetree does not specify any value for `common_soc_config.chipset_lockdown` Update the devicetree in early ramstage to always use `CHIPSET_LOCKDOWN_COREBOOT`, bypassing the mainboards' devicetree choice. Since all Skylake mainboards already use `CHIPSET_LOCKDOWN_COREBOOT`, this change is a no-op. Change-Id: I24a1a2fab166aa3bfe8e0b07f155f57f2bf745e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/52096/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0ae98a9..2a7c02a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootsplash.h> +#include <bootstate.h> #include <cbmem.h> #include <fsp/api.h> #include <acpi/acpi.h> @@ -220,6 +221,15 @@ .init = &soc_init_pre_device, }; +/* Update devicetree in earliest ramstage to always use CHIPSET_LOCKDOWN_COREBOOT */ +static void override_lockdown_config(void *unused) +{ + struct soc_intel_skylake_config *config = config_of_soc(); + config->common_soc_config.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT; +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, override_lockdown_config, NULL); + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a1a2fab166aa3bfe8e0b07f155f57f2bf745e3 Gerrit-Change-Number: 52096 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/kblrvp: Always use `CHIPSET_LOCKDOWN_COREBOOT`
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52095 ) Change subject: mb/intel/kblrvp: Always use `CHIPSET_LOCKDOWN_COREBOOT` ...................................................................... mb/intel/kblrvp: Always use `CHIPSET_LOCKDOWN_COREBOOT` Two of the variants used `CHIPSET_LOCKDOWN_COREBOOT`, whereas the other half used `CHIPSET_LOCKDOWN_FSP` by omission. Since this is most likely not done on purpose, choose `CHIPSET_LOCKDOWN_COREBOOT` on all variants for consistency. Now, all Skylake mainboards use `CHIPSET_LOCKDOWN_COREBOOT`. Change-Id: I2db1456d1734b2c0a6019002c211f608bcdf4a19 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb 4 files changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52095/1 diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b7..147a27a 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -110,6 +110,11 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index ad7c4ab..bc4a677 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -105,11 +105,6 @@ .tdp_pl2_override = 60, }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 397155b..b1d2917 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -110,11 +110,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 05.0 on end # SA IMGU device pci 14.3 on end # Camera diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 20c147c..e7e430d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -152,11 +152,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/52095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db1456d1734b2c0a6019002c211f608bcdf4a19 Gerrit-Change-Number: 52095 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: Choose `CHIPSET_LOCKDOWN_COREBOOT`
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52094 ) Change subject: mb/asrock/h110m: Choose `CHIPSET_LOCKDOWN_COREBOOT` ...................................................................... mb/asrock/h110m: Choose `CHIPSET_LOCKDOWN_COREBOOT` The `chipset_lockdown` option defaults to `CHIPSET_LOCKDOWN_FSP` if omitted. As most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, choose it here as well for consistency. Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/52094/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 4cb8735..74e5720 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -42,6 +42,10 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/52094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c Gerrit-Change-Number: 52094 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: add lalala variant
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Martin Roth, Paul Menzel, Aaron Durbin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52031 ) Change subject: mb/google/dedede: add lalala variant ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/dedede/variants/lalala/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52031/comment/e07a6083_7f00b988 PS2, Line 11: TBD Hm? https://review.coreboot.org/c/coreboot/+/52031/comment/e4d6f680_9bfc4744 PS2, Line 300: device pci 1c.7 on nit: I'd move this device up, so that the dev.func numbers are in order -- To view, visit https://review.coreboot.org/c/coreboot/+/52031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Gerrit-Change-Number: 52031 Gerrit-PatchSet: 2 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 12:53:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: add discrete TPM 2.0 configuration
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Aaron Durbin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52030 ) Change subject: mb/google/dedede: add discrete TPM 2.0 configuration ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/dedede/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52030/comment/f0886974_a18a3f60 PS2, Line 83: PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), To avoid preprocessor usage, I would extract GSPI1 pad config into two arrays, and program the corresponding array according to `CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)`. -- To view, visit https://review.coreboot.org/c/coreboot/+/52030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba Gerrit-Change-Number: 52030 Gerrit-PatchSet: 2 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sun, 04 Apr 2021 12:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... soc/intel: Do not bridge I/O resources with base=0 to LPC When the base of an I/O resource is zero, it usually means the resource is not used. Skip trying to bridge them to LPC to avoid wasting LPC I/O decode windows, of which there aren't many to begin with. Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/lpc/lpc_lib.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/52093/1 diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 73a4727..cff691c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -75,6 +75,9 @@ printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n", base, size); + if (base == 0) + return; + bridged_size = 0; bridge_base = base; -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/ti/am335x/mmc.c: Fix memset length argument
by Angel Pons (Code Review) 04 Apr '21

04 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52054 ) Change subject: soc/ti/am335x/mmc.c: Fix memset length argument ...................................................................... soc/ti/am335x/mmc.c: Fix memset length argument The sizeof() operator was being applied to a pointer-to-struct type. Correct this, so that the entire struct space gets cleared. Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Found-by: Coverity CID 1451732 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Sam Lewis <sam.vr.lewis(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/ti/am335x/mmc.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved Sam Lewis: Looks good to me, but someone else must approve diff --git a/src/soc/ti/am335x/mmc.c b/src/soc/ti/am335x/mmc.c index 395cf4f..b7b4f97 100644 --- a/src/soc/ti/am335x/mmc.c +++ b/src/soc/ti/am335x/mmc.c @@ -260,7 +260,7 @@ int err = 0; struct sd_mmc_ctrlr *mmc_ctrlr = &mmc_host->sd_mmc_ctrlr; - memset(mmc_ctrlr, 0, sizeof(mmc_ctrlr)); + memset(mmc_ctrlr, 0, sizeof(*mmc_ctrlr)); err = am335x_mmc_init(mmc_host->reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/52054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Gerrit-Change-Number: 52054 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/ti/am335x/mmc.c: Fix memset length argument
by Sam Lewis (Code Review) 04 Apr '21

04 Apr '21

Attention is currently required from: Angel Pons. Sam Lewis has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52054 ) Change subject: soc/ti/am335x/mmc.c: Fix memset length argument ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0 Gerrit-Change-Number: 52054 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 04 Apr 2021 06:22:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c: sx9310: add debouncer_depths attributes
by Gwendal Grignou (Code Review) 04 Apr '21

04 Apr '21

Gwendal Grignou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51892 ) Change subject: drivers/i2c: sx9310: add debouncer_depths attributes ...................................................................... Abandoned After talking with sboyd@, I will use cros_config. See src/platform2/chromeos-config/cros_config_host/cros_config_schema.yaml. -- To view, visit https://review.coreboot.org/c/coreboot/+/51892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10abf741b35c4443996b0a3a0c97433a9e9b4369 Gerrit-Change-Number: 51892 Gerrit-PatchSet: 8 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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coreboot-gerrit April 2021