April 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... nb/intel/sandybridge: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/stout/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_common.c 8 files changed, 3 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 5461b15..73dce98 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -33,8 +33,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 18ed380..2627fae 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0x0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b4d3800..5f1ea6b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21f9 inherit diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index de91bba..e0557ca 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0f3ee5c..6cda62b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -31,8 +31,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on ioapic_irq 4 INTA 0x10 ioapic_irq 4 INTB 0x11 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 20c994e..6f49cfe 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 824af3e..99d9763 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -43,11 +43,6 @@ struct i915_gpu_controller_info gfx; - /* - * Maximum PCI MMIO size in MiB. - */ - u16 pci_mmio_size; - /* Data for RAM init */ /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 72621e3..c7273ad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -338,24 +338,6 @@ } } -#define DEFAULT_PCI_MMIO_SIZE 2048 - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} - /* * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. * The ME/PCU/.. has the ability to change this. @@ -382,6 +364,8 @@ return !(reg32 & (1 << 25)); } +#define DEFAULT_PCI_MMIO_SIZE 2048 + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; @@ -389,7 +373,7 @@ size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; - mmiosize = get_mmio_size(); + mmiosize = DEFAULT_PCI_MMIO_SIZE; ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sandybridge boards: Drop default `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52071 ) Change subject: sandybridge boards: Drop default `pci_mmio_size` ...................................................................... sandybridge boards: Drop default `pci_mmio_size` 2 GiB is the default already. Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/asus/p8z77-v_lx2/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 16 files changed, 0 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 5050758..ee192cf 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 7b90149..22b474d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index eddca81..73671ee 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 969169c..60e54ae 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 0fc6dc1..40f8e6d 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1043 0x84ca inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 118a58e..9dc6a7c 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 0c24a9d..d753411 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1458 0x5000 inherit device pci 00.0 on # Host bridge diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index d0ec09c..479d813 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index fbff203..db902be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 61535df..f1ec5e7 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index ffd1d24..441abf2b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4b956757..6b7c6a2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index d9ececa..925bfb9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21fb inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 296be73..48d5791 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 7adc0f5..23744e1 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21f6 inherit diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 3f1934d..de0c9a2 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21db inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/52071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Gerrit-Change-Number: 52071 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/raminit.c 5 files changed, 1 insertion(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index af770dc..5f167df 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543d..e142a1c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b57b3fe..d5f96cb 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bc..ab589ea 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073dda..34e5657 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096) -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/dram/ddr3: Drop unused MRS helpers
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47343 ) Change subject: device/dram/ddr3: Drop unused MRS helpers ...................................................................... device/dram/ddr3: Drop unused MRS helpers These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h 2 files changed, 0 insertions(+), 353 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47343/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index ab6d828..16a76a2 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -638,226 +638,3 @@ printk(BIOS_INFO, " tCMDmin : %3u\n", DIV_ROUND_UP(dimm->tCMD, 256)); } - -/*============================================================================== - *= DDR3 MRS helpers - *----------------------------------------------------------------------------*/ - -/* - * MRS command structure: - * cmd[15:0] = Address pins MA[15:0] - * cmd[18:16] = Bank address BA[2:0] - */ - -/* Map tWR value to a bitmask of the MR0 cycle */ -static u16 ddr3_twr_to_mr0_map(u8 twr) -{ - if ((twr >= 5) && (twr <= 8)) - return (twr - 4) << 9; - - /* - * From 8T onwards, we can only use even values. Round up if we are - * given an odd value. - */ - if ((twr >= 9) && (twr <= 14)) - return ((twr + 1) >> 1) << 9; - - /* tWR == 16T is [000] */ - return 0; -} - -/* Map the CAS latency to a bitmask for the MR0 cycle */ -static u16 ddr3_cas_to_mr0_map(u8 cas) -{ - u16 mask = 0; - /* A[6:4] are bits [2:0] of (CAS - 4) */ - mask = ((cas - 4) & 0x07) << 4; - - /* A2 is the MSB of (CAS - 4) */ - if ((cas - 4) & (1 << 3)) - mask |= (1 << 2); - - return mask; -} - -/** - * \brief Get command address for a DDR3 MR0 command - * - * The DDR3 specification only covers odd write_recovery up to 7T. If an odd - * write_recovery greater than 7 is specified, it will be rounded up. If a tWR - * greater than 8 is specified, it is recommended to explicitly round it up or - * down before calling this function. - * - * write_recovery and cas are given in clock cycles. For example, a CAS of 7T - * should be given as 7. - * - * @param precharge_pd - * @param write_recovery Write recovery latency, tWR in clock cycles. - * @param dll_reset - * @param mode - * @param cas CAS latency in clock cycles. - * @param burst_type - * @param burst_length - */ -mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type burst_type, - enum ddr3_mr0_burst_length burst_length) -{ - mrs_cmd_t cmd = 0 << 16; - - if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) - cmd |= (1 << 12); - - cmd |= ddr3_twr_to_mr0_map(write_recovery); - - if (dll_reset == DDR3_MR0_DLL_RESET_YES) - cmd |= (1 << 8); - - if (mode == DDR3_MR0_MODE_TEST) - cmd |= (1 << 7); - - cmd |= ddr3_cas_to_mr0_map(cas); - - if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) - cmd |= (1 << 3); - - cmd |= (burst_length & 0x03) << 0; - - return cmd; -} - -static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) -{ - u16 mask = 0; - /* A9 <-> rtt_nom[2] */ - if (rtt_nom & (1 << 2)) - mask |= (1 << 9); - /* A6 <-> rtt_nom[1] */ - if (rtt_nom & (1 << 1)) - mask |= (1 << 6); - /* A2 <-> rtt_nom[0] */ - if (rtt_nom & (1 << 0)) - mask |= (1 << 2); - - return mask; -} - -static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) -{ - u16 mask = 0; - /* A5 <-> ods[1] */ - if (ods & (1 << 1)) - mask |= (1 << 5); - /* A1 <-> ods[0] */ - if (ods & (1 << 0)) - mask |= (1 << 1); - - return mask; -} - -/** - * \brief Get command address for a DDR3 MR1 command - */ -mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods ods, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable) -{ - mrs_cmd_t cmd = 1 << 16; - - if (qoff == DDR3_MR1_QOFF_DISABLE) - cmd |= (1 << 12); - - if (tqds == DDR3_MR1_TQDS_ENABLE) - cmd |= (1 << 11); - - cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); - - if (write_leveling == DDR3_MR1_WRLVL_ENABLE) - cmd |= (1 << 7); - - cmd |= ddr3_ods_to_mr1_map(ods); - - cmd |= (additive_latency & 0x03) << 3; - - if (dll_disable == DDR3_MR1_DLL_DISABLE) - cmd |= (1 << 0); - - return cmd; -} - -/** - * \brief Get command address for a DDR3 MR2 command - * - * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be - * given as 7. - * - * @param rtt_wr - * @param extended_temp - * @param self_refresh - * @param cas_cwl CAS write latency in clock cycles. - */ - -mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl) -{ - mrs_cmd_t cmd = 2 << 16; - - cmd |= (rtt_wr & 0x03) << 9; - - if (extended_temp == DDR3_MR2_SRT_EXTENDED) - cmd |= (1 << 7); - - if (self_refresh == DDR3_MR2_ASR_AUTO) - cmd |= (1 << 6); - - cmd |= ((cas_cwl - 5) & 0x07) << 3; - - return cmd; -} - -/** - * \brief Get command address for a DDR3 MR3 command - * - * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read - * leveling mode. Zero for normal operation. - */ -mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) -{ - mrs_cmd_t cmd = 3 << 16; - - if (dataflow_from_mpr) - cmd |= (1 << 2); - - return cmd; -} - -/** - * \brief Mirror the address bits for this MRS command - * - * Swap the following bits in the MRS command: - * - MA3 <-> MA4 - * - MA5 <-> MA6 - * - MA7 <-> MA8 - * - BA0 <-> BA1 - */ -mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) -{ - u32 downshift, upshift; - /* High bits= A4 | A6 | A8 | BA1 */ - /* Low bits = A3 | A5 | A7 | BA0 */ - u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); - downshift = (cmd & (lowbits << 1)); - upshift = (cmd & lowbits); - cmd &= ~(lowbits | (lowbits << 1)); - cmd |= (downshift >> 1) | (upshift << 1); - return cmd; -} diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0814990..4a5134f 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -181,135 +181,5 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, const dimm_attr *info); -/** - * \brief Read double word from specified address - * - * Should be useful when doing an MRS to the DIMM - */ -static inline u32 volatile_read(volatile uintptr_t addr) -{ - volatile u32 result; - result = *(volatile u32 *)addr; - return result; -} - -/** - * \brief Representation of an MRS command - * - * This represents an MRS command as seen by the DIMM. This is not a memory - * address that can be read to generate an MRS command. The mapping of CPU - * to memory pins is hardware-dependent. - * \n - * The idea is to generalize the MRS code, and only need a hardware-specific - * function to map the MRS bits to CPU address bits. An MRS command can be - * sent like: - * @code{.c} - * u32 addr; - * mrs_cmd_t mrs; - * chipset_enable_mrs_command_mode(); - * mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl) - * if (rank_has_mirrorred_pins) - * mrs = ddr3_mrs_mirror_pins(mrs); - * addr = chipset_specific_get_mrs_addr(mrs); - * volatile_read(addr); - * @endcode - * - * The MRS representation has the following structure: - * - cmd[15:0] = Address pins MA[15:0] - * - cmd[18:16] = Bank address BA[2:0] - */ -typedef u32 mrs_cmd_t; - -enum ddr3_mr0_precharge { - DDR3_MR0_PRECHARGE_SLOW = 0, - DDR3_MR0_PRECHARGE_FAST = 1, -}; -enum ddr3_mr0_mode { - DDR3_MR0_MODE_NORMAL = 0, - DDR3_MR0_MODE_TEST = 1, -}; -enum ddr3_mr0_dll_reset { - DDR3_MR0_DLL_RESET_NO = 0, - DDR3_MR0_DLL_RESET_YES = 1, -}; -enum ddr3_mr0_burst_type { - DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, - DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, -}; -enum ddr3_mr0_burst_length { - DDR3_MR0_BURST_LENGTH_8 = 0, - DDR3_MR0_BURST_LENGTH_CHOP = 1, - DDR3_MR0_BURST_LENGTH_4 = 2, -}; -mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type interleaved_burst, - enum ddr3_mr0_burst_length burst_length); - -enum ddr3_mr1_qoff { - DDR3_MR1_QOFF_ENABLE = 0, - DDR3_MR1_QOFF_DISABLE = 1, -}; -enum ddr3_mr1_tqds { - DDR3_MR1_TQDS_DISABLE = 0, - DDR3_MR1_TQDS_ENABLE = 1, -}; -enum ddr3_mr1_write_leveling { - DDR3_MR1_WRLVL_DISABLE = 0, - DDR3_MR1_WRLVL_ENABLE = 1, -}; -enum ddr3_mr1_rtt_nom { - DDR3_MR1_RTT_NOM_OFF = 0, - DDR3_MR1_RTT_NOM_RZQ4 = 1, - DDR3_MR1_RTT_NOM_RZQ2 = 2, - DDR3_MR1_RTT_NOM_RZQ6 = 3, - DDR3_MR1_RTT_NOM_RZQ12 = 4, - DDR3_MR1_RTT_NOM_RZQ8 = 5, -}; -enum ddr3_mr1_additive_latency { - DDR3_MR1_AL_DISABLE = 0, - DDR3_MR1_AL_CL_MINUS_1 = 1, - DDR3_MR1_AL_CL_MINUS_2 = 2, -}; -enum ddr3_mr1_ods { - DDR3_MR1_ODS_RZQ6 = 0, - DDR3_MR1_ODS_RZQ7 = 1, -}; -enum ddr3_mr1_dll { - DDR3_MR1_DLL_ENABLE = 0, - DDR3_MR1_DLL_DISABLE = 1, -}; - -mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods output_drive_strenght, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable); - -enum ddr3_mr2_rttwr { - DDR3_MR2_RTTWR_OFF = 0, - DDR3_MR2_RTTWR_RZQ4 = 1, - DDR3_MR2_RTTWR_RZQ2 = 2, -}; -enum ddr3_mr2_srt_range { - DDR3_MR2_SRT_NORMAL = 0, - DDR3_MR2_SRT_EXTENDED = 1, -}; -enum ddr3_mr2_asr { - DDR3_MR2_ASR_MANUAL = 0, - DDR3_MR2_ASR_AUTO = 1, -}; - -mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl); - -mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); -mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); #endif /* DEVICE_DRAM_DDR3L_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Gerrit-Change-Number: 47343 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: nb/intel/sandybridge: Rename `pdwm_mode` enum
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51901 ) Change subject: nb/intel/sandybridge: Rename `pdwm_mode` enum ...................................................................... nb/intel/sandybridge: Rename `pdwm_mode` enum The `pdwm` part was supposed to be an abbreviation of `power down`, but it is neither self-explanatory nor properly-spelled. Rename the enum. Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 687386d..72621e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -684,7 +684,7 @@ } /* Obtain optimal power down mode for current configuration */ -static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) { if (ctrl->tXP > 8) return PDM_NONE; @@ -703,7 +703,7 @@ u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum pdwm_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 1622259..c24b3a0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -306,7 +306,7 @@ */ #define MRC_CACHE_VERSION 5 -enum pdwm_mode { +enum power_down_mode { PDM_NONE = 0, PDM_APD = 1, PDM_PPD = 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/51901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874 Gerrit-Change-Number: 51901 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: spd.h: Remove unused definitions
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51900 ) Change subject: spd.h: Remove unused definitions ...................................................................... spd.h: Remove unused definitions These definitions are unused and not particularly useful. Drop them. Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/spd.h 1 file changed, 0 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/include/spd.h b/src/include/spd.h index 9afb706..9695932 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -207,72 +207,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - /* Byte 3: Module type information */ #define SPD_UNDEFINED 0x00 #define SPD_RDIMM 0x01 -- To view, visit https://review.coreboot.org/c/coreboot/+/51900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Gerrit-Change-Number: 51900 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945/raminit.c: Replace `DIMM0`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52073 ) Change subject: nb/intel/i945/raminit.c: Replace `DIMM0` ...................................................................... nb/intel/i945/raminit.c: Replace `DIMM0` Use the actual value as it is more informative. Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6b1bdb9..ce620ac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -45,7 +45,7 @@ if (sysinfo->spd_addresses) return sysinfo->spd_addresses[device]; else - return DIMM0 + device; + return 0x50 + device; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Gerrit-Change-Number: 52073 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb/intel/i945: Refactor `dump_spd_registers` function
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51899 ) Change subject: nb/intel/i945: Refactor `dump_spd_registers` function ...................................................................... nb/intel/i945: Refactor `dump_spd_registers` function Use the mainboard-provided SPD map and skip unused addresses. Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/romstage.c 3 files changed, 10 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index db987ca..6073f59 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -57,11 +57,13 @@ } } -void dump_spd_registers(void) +void dump_spd_registers(u8 spd_map[4]) { - unsigned int device; - device = DIMM0; - while (device <= DIMM3) { + for (unsigned int d = 0; d < 4; d++) { + const unsigned int device = spd_map[d]; + if (device == 0) + continue; + int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); @@ -76,7 +78,6 @@ } printk(BIOS_DEBUG, "%02x ", status); } - device++; printk(BIOS_DEBUG, "\n"); } } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe06afc..d8993ac 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -337,7 +337,7 @@ void print_pci_devices(void); void dump_pci_device(unsigned int dev); void dump_pci_devices(void); -void dump_spd_registers(void); +void dump_spd_registers(u8 spd_map[4]); void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 248fe14..22eae4e 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -48,11 +48,11 @@ mainboard_pre_raminit_config(s3resume); - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - mainboard_get_spd_map(spd_map); + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(spd_map); + sdram_initialize(s3resume ? BOOT_PATH_RESUME : BOOT_PATH_NORMAL, spd_map); /* This should probably go away. Until now it is required -- To view, visit https://review.coreboot.org/c/coreboot/+/51899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Gerrit-Change-Number: 51899 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/dram/ddr4.h: Align with DDR3 and DDR2
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51898 ) Change subject: device/dram/ddr4.h: Align with DDR3 and DDR2 ...................................................................... device/dram/ddr4.h: Align with DDR3 and DDR2 Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/dram/ddr4.c M src/include/device/dram/ddr4.h 2 files changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index e670b20..cc66dcc 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -163,7 +163,7 @@ * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; @@ -261,7 +261,7 @@ } enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info) + const struct dimm_attr_ddr4_st *info) { struct memory_info *mem_info; struct dimm_info *dimm; @@ -298,16 +298,16 @@ dimm->mod_id = info->manufacturer_id; switch (info->dimm_type) { - case SPD_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: dimm->mod_type = SPD_SODIMM; break; - case SPD_DIMM_TYPE_72B_SO_RDIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: dimm->mod_type = SPD_72B_SO_RDIMM; break; - case SPD_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: dimm->mod_type = SPD_UDIMM; break; - case SPD_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: dimm->mod_type = SPD_RDIMM; break; default: diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index eac8bf8..ee7a1ea 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -25,20 +25,20 @@ * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. */ -enum spd_dimm_type { - SPD_DIMM_TYPE_EXTENDED = 0x0, - SPD_DIMM_TYPE_RDIMM = 0x1, - SPD_DIMM_TYPE_UDIMM = 0x2, - SPD_DIMM_TYPE_SO_DIMM = 0x3, - SPD_DIMM_TYPE_LRDIMM = 0x4, - SPD_DIMM_TYPE_MINI_RDIMM = 0x5, - SPD_DIMM_TYPE_MINI_UDIMM = 0x6, - SPD_DIMM_TYPE_72B_SO_RDIMM = 0x8, - SPD_DIMM_TYPE_72B_SO_UDIMM = 0x9, - SPD_DIMM_TYPE_16B_SO_DIMM = 0xc, - SPD_DIMM_TYPE_32B_SO_DIMM = 0xd, +enum spd_dimm_type_ddr4 { + SPD_DDR4_DIMM_TYPE_EXTENDED = 0x0, + SPD_DDR4_DIMM_TYPE_RDIMM = 0x1, + SPD_DDR4_DIMM_TYPE_UDIMM = 0x2, + SPD_DDR4_DIMM_TYPE_SO_DIMM = 0x3, + SPD_DDR4_DIMM_TYPE_LRDIMM = 0x4, + SPD_DDR4_DIMM_TYPE_MINI_RDIMM = 0x5, + SPD_DDR4_DIMM_TYPE_MINI_UDIMM = 0x6, + SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM = 0x8, + SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM = 0x9, + SPD_DDR4_DIMM_TYPE_16B_SO_DIMM = 0xc, + SPD_DDR4_DIMM_TYPE_32B_SO_DIMM = 0xd, /* Masks to bits 3:0 to give the dimm type */ - SPD_DIMM_TYPE_MASK = 0xf + SPD_DDR4_DIMM_TYPE_MASK = 0xf }; /** @@ -46,9 +46,9 @@ * * The characteristics of each DIMM, as presented by the SPD */ -typedef struct dimm_attr_st { +struct dimm_attr_ddr4_st { enum spd_memory_type dram_type; - enum spd_dimm_type dimm_type; + enum spd_dimm_type_ddr4 dimm_type; char part_number[SPD_DDR4_PART_LEN + 1]; u8 serial_number[4]; u8 bus_width; @@ -59,15 +59,15 @@ u16 manufacturer_id; u16 vdd_voltage; bool ecc_extension; -} dimm_attr; +}; typedef u8 spd_raw_data[512]; -int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info); + const struct dimm_attr_ddr4_st *info); /** * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s -- To view, visit https://review.coreboot.org/c/coreboot/+/51898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Gerrit-Change-Number: 51898 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: include/spd_ddr2.h: Remove unused and redundant file
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51897 ) Change subject: include/spd_ddr2.h: Remove unused and redundant file ...................................................................... include/spd_ddr2.h: Remove unused and redundant file DDR2-related definitions exist in `device/dram/ddr2` already. Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51897 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/include/spd_ddr2.h 1 file changed, 0 insertions(+), 104 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h deleted file mode 100644 index 98c689f..0000000 --- a/src/include/spd_ddr2.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SPD_DDR2_H__ -#define __SPD_DDR2_H__ - -/* SPDs for DDR2 SDRAM */ -#define SPD_MEM_TYPE 2 - #define SPD_MEM_TYPE_SDRAM_DDR 0x07 - #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 - -#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ - #define SPD_DIMM_TYPE_RDIMM 0x01 - #define SPD_DIMM_TYPE_UDIMM 0x02 - #define SPD_DIMM_TYPE_SODIMM 0x04 - #define SPD_72B_SO_CDIMM 0x06 - #define SPD_72B_SO_RDIMM 0x07 - #define SPD_DIMM_TYPE_uDIMM 0x08 - #define SPD_DIMM_TYPE_mRDIMM 0x10 - #define SPD_DIMM_TYPE_mUDIMM 0x20 - -#define SPD_MOD_ATTRIB 21 - #define SPD_MOD_ATTRIB_DIFCK 0x20 - #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ - #define SPD_MOD_ATTRIB_PROBE 0x40 - -#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ -#define SPD_DIMM_CONF_TYPE 11 - #define SPD_DIMM_CONF_TYPE_ECC 0x02 - #define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */ - -#define SPD_CAS_LAT_MIN_X_1 23 -#define SPD_CAS_LAT_MAX_X_1 24 -#define SPD_CAS_LAT_MIN_X_2 25 -#define SPD_CAS_LAT_MAX_X_2 26 - -#define SPD_BURST_LENGTHS 16 - #define SPD_BURST_LENGTHS_4 (1<<2) - #define SPD_BURST_LENGTHS_8 (1<<3) - -#define SPD_ROW_NUM 3 /* Number of Row addresses */ -#define SPD_COL_NUM 4 /* Number of Column addresses */ -#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on - SDRAM device, it could be 0x4, 0x8, so address - lines for that would be 2, and 3 */ - -/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planar), - * Height bit[7:5] - */ -#define SPD_MOD_ATTRIB_RANK 5 - #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 - #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 - #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 - #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 - #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 - -#define SPD_RANK_SIZE 31 /* Only one bit is set */ - #define SPD_RANK_SIZE_1GB (1<<0) - #define SPD_RANK_SIZE_2GB (1<<1) - #define SPD_RANK_SIZE_4GB (1<<2) - #define SPD_RANK_SIZE_8GB (1<<3) - #define SPD_RANK_SIZE_16GB (1<<4) - #define SPD_RANK_SIZE_128MB (1<<5) - #define SPD_RANK_SIZE_256MB (1<<6) - #define SPD_RANK_SIZE_512MB (1<<7) - -/* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ -#define SPD_DATA_WIDTH 6 -/* Primary SDRAM Width, it could be 0x08 or 0x10 */ -#define SPD_PRI_WIDTH 13 -/* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ -#define SPD_ERR_WIDTH 14 - -#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ - #define SPD_CAS_LAT_2 (1<<2) - #define SPD_CAS_LAT_3 (1<<3) - #define SPD_CAS_LAT_4 (1<<4) - #define SPD_CAS_LAT_5 (1<<5) - #define SPD_CAS_LAT_6 (1<<6) - #define SPD_CAS_LAT_7 (1<<7) - -/* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) - * + (val & 3) * 0.25)ns - */ -#define SPD_TRP 27 -#define SPD_TRRD 28 -#define SPD_TRCD 29 -#define SPD_TRAS 30 -#define SPD_TWR 36 /* x */ -#define SPD_TWTR 37 /* x */ -#define SPD_TRTP 38 /* x */ - -#define SPD_EX_TRC_TRFC 40 -/* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] - * ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0} - */ -#define SPD_TRC 41 -/* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] - * + (val40 & 1)*256 - */ -#define SPD_TRFC 42 - -#define SPD_TREF 12 - -#endif /* __SPD_DDR2_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20 Gerrit-Change-Number: 51897 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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