coreboot-gerrit April 2021

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Change in coreboot[master]: spd.h: Remove unused definitions
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51900 ) Change subject: spd.h: Remove unused definitions ...................................................................... spd.h: Remove unused definitions These definitions are unused and not particularly useful. Drop them. Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/spd.h 1 file changed, 0 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/include/spd.h b/src/include/spd.h index 9afb706..9695932 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -207,72 +207,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - /* Byte 3: Module type information */ #define SPD_UNDEFINED 0x00 #define SPD_RDIMM 0x01 -- To view, visit https://review.coreboot.org/c/coreboot/+/51900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae Gerrit-Change-Number: 51900 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945/raminit.c: Replace `DIMM0`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52073 ) Change subject: nb/intel/i945/raminit.c: Replace `DIMM0` ...................................................................... nb/intel/i945/raminit.c: Replace `DIMM0` Use the actual value as it is more informative. Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6b1bdb9..ce620ac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -45,7 +45,7 @@ if (sysinfo->spd_addresses) return sysinfo->spd_addresses[device]; else - return DIMM0 + device; + return 0x50 + device; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7 Gerrit-Change-Number: 52073 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945: Refactor `dump_spd_registers` function
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51899 ) Change subject: nb/intel/i945: Refactor `dump_spd_registers` function ...................................................................... nb/intel/i945: Refactor `dump_spd_registers` function Use the mainboard-provided SPD map and skip unused addresses. Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/romstage.c 3 files changed, 10 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index db987ca..6073f59 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -57,11 +57,13 @@ } } -void dump_spd_registers(void) +void dump_spd_registers(u8 spd_map[4]) { - unsigned int device; - device = DIMM0; - while (device <= DIMM3) { + for (unsigned int d = 0; d < 4; d++) { + const unsigned int device = spd_map[d]; + if (device == 0) + continue; + int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); @@ -76,7 +78,6 @@ } printk(BIOS_DEBUG, "%02x ", status); } - device++; printk(BIOS_DEBUG, "\n"); } } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe06afc..d8993ac 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -337,7 +337,7 @@ void print_pci_devices(void); void dump_pci_device(unsigned int dev); void dump_pci_devices(void); -void dump_spd_registers(void); +void dump_spd_registers(u8 spd_map[4]); void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 248fe14..22eae4e 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -48,11 +48,11 @@ mainboard_pre_raminit_config(s3resume); - if (CONFIG(DEBUG_RAM_SETUP)) - dump_spd_registers(); - mainboard_get_spd_map(spd_map); + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(spd_map); + sdram_initialize(s3resume ? BOOT_PATH_RESUME : BOOT_PATH_NORMAL, spd_map); /* This should probably go away. Until now it is required -- To view, visit https://review.coreboot.org/c/coreboot/+/51899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b71cff290343c1000d5613209049fa9724e3d Gerrit-Change-Number: 51899 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/dram/ddr4.h: Align with DDR3 and DDR2
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51898 ) Change subject: device/dram/ddr4.h: Align with DDR3 and DDR2 ...................................................................... device/dram/ddr4.h: Align with DDR3 and DDR2 Drop unnecessary typedefs and rename DDR4-specific definitions to avoid name clashes, as done for DDR3 in earlier commits. This allows including and using both DDR3 and DDR4 headers in the same compilation unit. Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/dram/ddr4.c M src/include/device/dram/ddr4.h 2 files changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index e670b20..cc66dcc 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -163,7 +163,7 @@ * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; @@ -261,7 +261,7 @@ } enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info) + const struct dimm_attr_ddr4_st *info) { struct memory_info *mem_info; struct dimm_info *dimm; @@ -298,16 +298,16 @@ dimm->mod_id = info->manufacturer_id; switch (info->dimm_type) { - case SPD_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: dimm->mod_type = SPD_SODIMM; break; - case SPD_DIMM_TYPE_72B_SO_RDIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: dimm->mod_type = SPD_72B_SO_RDIMM; break; - case SPD_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: dimm->mod_type = SPD_UDIMM; break; - case SPD_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: dimm->mod_type = SPD_RDIMM; break; default: diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index eac8bf8..ee7a1ea 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -25,20 +25,20 @@ * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. */ -enum spd_dimm_type { - SPD_DIMM_TYPE_EXTENDED = 0x0, - SPD_DIMM_TYPE_RDIMM = 0x1, - SPD_DIMM_TYPE_UDIMM = 0x2, - SPD_DIMM_TYPE_SO_DIMM = 0x3, - SPD_DIMM_TYPE_LRDIMM = 0x4, - SPD_DIMM_TYPE_MINI_RDIMM = 0x5, - SPD_DIMM_TYPE_MINI_UDIMM = 0x6, - SPD_DIMM_TYPE_72B_SO_RDIMM = 0x8, - SPD_DIMM_TYPE_72B_SO_UDIMM = 0x9, - SPD_DIMM_TYPE_16B_SO_DIMM = 0xc, - SPD_DIMM_TYPE_32B_SO_DIMM = 0xd, +enum spd_dimm_type_ddr4 { + SPD_DDR4_DIMM_TYPE_EXTENDED = 0x0, + SPD_DDR4_DIMM_TYPE_RDIMM = 0x1, + SPD_DDR4_DIMM_TYPE_UDIMM = 0x2, + SPD_DDR4_DIMM_TYPE_SO_DIMM = 0x3, + SPD_DDR4_DIMM_TYPE_LRDIMM = 0x4, + SPD_DDR4_DIMM_TYPE_MINI_RDIMM = 0x5, + SPD_DDR4_DIMM_TYPE_MINI_UDIMM = 0x6, + SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM = 0x8, + SPD_DDR4_DIMM_TYPE_72B_SO_UDIMM = 0x9, + SPD_DDR4_DIMM_TYPE_16B_SO_DIMM = 0xc, + SPD_DDR4_DIMM_TYPE_32B_SO_DIMM = 0xd, /* Masks to bits 3:0 to give the dimm type */ - SPD_DIMM_TYPE_MASK = 0xf + SPD_DDR4_DIMM_TYPE_MASK = 0xf }; /** @@ -46,9 +46,9 @@ * * The characteristics of each DIMM, as presented by the SPD */ -typedef struct dimm_attr_st { +struct dimm_attr_ddr4_st { enum spd_memory_type dram_type; - enum spd_dimm_type dimm_type; + enum spd_dimm_type_ddr4 dimm_type; char part_number[SPD_DDR4_PART_LEN + 1]; u8 serial_number[4]; u8 bus_width; @@ -59,15 +59,15 @@ u16 manufacturer_id; u16 vdd_voltage; bool ecc_extension; -} dimm_attr; +}; typedef u8 spd_raw_data[512]; -int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info); + const struct dimm_attr_ddr4_st *info); /** * Converts DDR4 clock speed in MHz to the standard reported speed in MT/s -- To view, visit https://review.coreboot.org/c/coreboot/+/51898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0 Gerrit-Change-Number: 51898 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: include/spd_ddr2.h: Remove unused and redundant file
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51897 ) Change subject: include/spd_ddr2.h: Remove unused and redundant file ...................................................................... include/spd_ddr2.h: Remove unused and redundant file DDR2-related definitions exist in `device/dram/ddr2` already. Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51897 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/include/spd_ddr2.h 1 file changed, 0 insertions(+), 104 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h deleted file mode 100644 index 98c689f..0000000 --- a/src/include/spd_ddr2.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SPD_DDR2_H__ -#define __SPD_DDR2_H__ - -/* SPDs for DDR2 SDRAM */ -#define SPD_MEM_TYPE 2 - #define SPD_MEM_TYPE_SDRAM_DDR 0x07 - #define SPD_MEM_TYPE_SDRAM_DDR2 0x08 - -#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/ - #define SPD_DIMM_TYPE_RDIMM 0x01 - #define SPD_DIMM_TYPE_UDIMM 0x02 - #define SPD_DIMM_TYPE_SODIMM 0x04 - #define SPD_72B_SO_CDIMM 0x06 - #define SPD_72B_SO_RDIMM 0x07 - #define SPD_DIMM_TYPE_uDIMM 0x08 - #define SPD_DIMM_TYPE_mRDIMM 0x10 - #define SPD_DIMM_TYPE_mUDIMM 0x20 - -#define SPD_MOD_ATTRIB 21 - #define SPD_MOD_ATTRIB_DIFCK 0x20 - #define SPD_MOD_ATTRIB_REGADC 0x11 /* x */ - #define SPD_MOD_ATTRIB_PROBE 0x40 - -#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */ -#define SPD_DIMM_CONF_TYPE 11 - #define SPD_DIMM_CONF_TYPE_ECC 0x02 - #define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */ - -#define SPD_CAS_LAT_MIN_X_1 23 -#define SPD_CAS_LAT_MAX_X_1 24 -#define SPD_CAS_LAT_MIN_X_2 25 -#define SPD_CAS_LAT_MAX_X_2 26 - -#define SPD_BURST_LENGTHS 16 - #define SPD_BURST_LENGTHS_4 (1<<2) - #define SPD_BURST_LENGTHS_8 (1<<3) - -#define SPD_ROW_NUM 3 /* Number of Row addresses */ -#define SPD_COL_NUM 4 /* Number of Column addresses */ -#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on - SDRAM device, it could be 0x4, 0x8, so address - lines for that would be 2, and 3 */ - -/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planar), - * Height bit[7:5] - */ -#define SPD_MOD_ATTRIB_RANK 5 - #define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0 - #define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07 - #define SPD_MOD_ATTRIB_RANK_NUM_BASE 1 - #define SPD_MOD_ATTRIB_RANK_NUM_MIN 1 - #define SPD_MOD_ATTRIB_RANK_NUM_MAX 8 - -#define SPD_RANK_SIZE 31 /* Only one bit is set */ - #define SPD_RANK_SIZE_1GB (1<<0) - #define SPD_RANK_SIZE_2GB (1<<1) - #define SPD_RANK_SIZE_4GB (1<<2) - #define SPD_RANK_SIZE_8GB (1<<3) - #define SPD_RANK_SIZE_16GB (1<<4) - #define SPD_RANK_SIZE_128MB (1<<5) - #define SPD_RANK_SIZE_256MB (1<<6) - #define SPD_RANK_SIZE_512MB (1<<7) - -/* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */ -#define SPD_DATA_WIDTH 6 -/* Primary SDRAM Width, it could be 0x08 or 0x10 */ -#define SPD_PRI_WIDTH 13 -/* Error Checking SDRAM Width, it could be 0x08 or 0x10 */ -#define SPD_ERR_WIDTH 14 - -#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */ - #define SPD_CAS_LAT_2 (1<<2) - #define SPD_CAS_LAT_3 (1<<3) - #define SPD_CAS_LAT_4 (1<<4) - #define SPD_CAS_LAT_5 (1<<5) - #define SPD_CAS_LAT_6 (1<<6) - #define SPD_CAS_LAT_7 (1<<7) - -/* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) - * + (val & 3) * 0.25)ns - */ -#define SPD_TRP 27 -#define SPD_TRRD 28 -#define SPD_TRCD 29 -#define SPD_TRAS 30 -#define SPD_TWR 36 /* x */ -#define SPD_TWTR 37 /* x */ -#define SPD_TRTP 38 /* x */ - -#define SPD_EX_TRC_TRFC 40 -/* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] - * ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0} - */ -#define SPD_TRC 41 -/* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] - * + (val40 & 1)*256 - */ -#define SPD_TRFC 42 - -#define SPD_TREF 12 - -#endif /* __SPD_DDR2_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I509f728138327d8a0a88e4503235f05bf14aed20 Gerrit-Change-Number: 51897 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: device/dram/ddr3: Rename DDR3 SPD memory types
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51896 ) Change subject: device/dram/ddr3: Rename DDR3 SPD memory types ...................................................................... device/dram/ddr3: Rename DDR3 SPD memory types To avoid name clashes with definitions for other DRAM generations, rename the enum type and values to contain `ddr3` or `DDR3`. Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h M src/soc/intel/common/smbios.c 3 files changed, 34 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index b38e0a1..d28bfbe 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -27,11 +27,11 @@ * * @param type DIMM type. This is byte[3] of the SPD. */ -int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) +int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type) { - if ((type == SPD_DIMM_TYPE_RDIMM) - | (type == SPD_DIMM_TYPE_MINI_RDIMM) - | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + if ((type == SPD_DDR3_DIMM_TYPE_RDIMM) + | (type == SPD_DDR3_DIMM_TYPE_MINI_RDIMM) + | (type == SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM)) return 1; return 0; @@ -544,22 +544,22 @@ dimm->mod_id = info->manufacturer_id; switch (info->dimm_type) { - case SPD_DIMM_TYPE_SO_DIMM: + case SPD_DDR3_DIMM_TYPE_SO_DIMM: dimm->mod_type = SPD_SODIMM; break; - case SPD_DIMM_TYPE_72B_SO_CDIMM: + case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: dimm->mod_type = SPD_72B_SO_CDIMM; break; - case SPD_DIMM_TYPE_72B_SO_RDIMM: + case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: dimm->mod_type = SPD_72B_SO_RDIMM; break; - case SPD_DIMM_TYPE_UDIMM: + case SPD_DDR3_DIMM_TYPE_UDIMM: dimm->mod_type = SPD_UDIMM; break; - case SPD_DIMM_TYPE_RDIMM: + case SPD_DDR3_DIMM_TYPE_RDIMM: dimm->mod_type = SPD_RDIMM; break; - case SPD_DIMM_TYPE_UNDEFINED: + case SPD_DDR3_DIMM_TYPE_UNDEFINED: default: dimm->mod_type = SPD_UNDEFINED; break; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6afcceb..17910ff 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -51,23 +51,23 @@ * Module type (byte 3, bits 3:0) of SPD * This definition is specific to DDR3. DDR2 SPDs have a different structure. */ -enum spd_dimm_type { - SPD_DIMM_TYPE_UNDEFINED = 0x00, - SPD_DIMM_TYPE_RDIMM = 0x01, - SPD_DIMM_TYPE_UDIMM = 0x02, - SPD_DIMM_TYPE_SO_DIMM = 0x03, - SPD_DIMM_TYPE_MICRO_DIMM = 0x04, - SPD_DIMM_TYPE_MINI_RDIMM = 0x05, - SPD_DIMM_TYPE_MINI_UDIMM = 0x06, - SPD_DIMM_TYPE_MINI_CDIMM = 0x07, - SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08, - SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09, - SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a, - SPD_DIMM_TYPE_LRDIMM = 0x0b, - SPD_DIMM_TYPE_16B_SO_DIMM = 0x0c, - SPD_DIMM_TYPE_32B_SO_DIMM = 0x0d, +enum spd_dimm_type_ddr3 { + SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DDR3_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR3_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR3_DIMM_TYPE_SO_DIMM = 0x03, + SPD_DDR3_DIMM_TYPE_MICRO_DIMM = 0x04, + SPD_DDR3_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR3_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR3_DIMM_TYPE_MINI_CDIMM = 0x07, + SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM = 0x0a, + SPD_DDR3_DIMM_TYPE_LRDIMM = 0x0b, + SPD_DDR3_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR3_DIMM_TYPE_32B_SO_DIMM = 0x0d, /* Masks to bits 3:0 to give the dimm type */ - SPD_DIMM_TYPE_MASK = 0x0f, + SPD_DDR3_DIMM_TYPE_MASK = 0x0f, }; /** @@ -120,7 +120,7 @@ */ struct dimm_attr_ddr3_st { enum spd_memory_type dram_type; - enum spd_dimm_type dimm_type; + enum spd_dimm_type_ddr3 dimm_type; u16 cas_supported; /* Flags extracted from SPD */ union dimm_flags_ddr3_st flags; @@ -173,7 +173,7 @@ u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); -int spd_dimm_is_registered_ddr3(enum spd_dimm_type type); +int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 5e3560c..9cbdecb 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -17,22 +17,22 @@ dimm->mod_id = mod_id; /* Translate to DDR2 module type field that SMBIOS code expects. */ switch (mod_type) { - case SPD_DIMM_TYPE_SO_DIMM: + case SPD_DDR3_DIMM_TYPE_SO_DIMM: dimm->mod_type = SPD_SODIMM; break; - case SPD_DIMM_TYPE_72B_SO_CDIMM: + case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM: dimm->mod_type = SPD_72B_SO_CDIMM; break; - case SPD_DIMM_TYPE_72B_SO_RDIMM: + case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM: dimm->mod_type = SPD_72B_SO_RDIMM; break; - case SPD_DIMM_TYPE_UDIMM: + case SPD_DDR3_DIMM_TYPE_UDIMM: dimm->mod_type = SPD_UDIMM; break; - case SPD_DIMM_TYPE_RDIMM: + case SPD_DDR3_DIMM_TYPE_RDIMM: dimm->mod_type = SPD_RDIMM; break; - case SPD_DIMM_TYPE_UNDEFINED: + case SPD_DDR3_DIMM_TYPE_UNDEFINED: default: dimm->mod_type = SPD_UNDEFINED; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/51896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8 Gerrit-Change-Number: 51896 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: device/dram/ddr3: Get rid of useless typedefs
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51895 ) Change subject: device/dram/ddr3: Get rid of useless typedefs ...................................................................... device/dram/ddr3: Get rid of useless typedefs These typedefs are not necessary. Remove them, and rename some elements to avoid any confusion with other DRAM generations, such as DDR4. Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/x4x/raminit.c M src/soc/intel/baytrail/romstage/raminit.c 7 files changed, 19 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index ab6d828..b38e0a1 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -98,7 +98,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) { int ret; u16 crc, spd_crc; @@ -394,7 +394,7 @@ * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_xmp_decode_ddr3(dimm_attr *dimm, +int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, enum ddr3_xmp_profile profile) { @@ -505,7 +505,7 @@ */ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info) + const struct dimm_attr_ddr3_st *info) { struct memory_info *mem_info; struct dimm_info *dimm; @@ -597,7 +597,7 @@ * * @param dimm pointer to already decoded @ref dimm_attr structure */ -void dram_print_spd_ddr3(const dimm_attr * dimm) +void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm) { u16 val16; int i; diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0814990..6afcceb 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -75,7 +75,7 @@ * * Characteristic flags for the DIMM, as presented by the SPD */ -typedef union dimm_flags_st { +union dimm_flags_ddr3_st { /* The whole point of the union/struct construct is to allow us to clear * all the bits with one line: flags.raw = 0. * We do not care how these bits are ordered */ @@ -111,19 +111,19 @@ unsigned int therm_sensor:1; }; unsigned int raw; -} dimm_flags_t; +}; /** * \brief DIMM characteristics * * The characteristics of each DIMM, as presented by the SPD */ -typedef struct dimm_attr_st { +struct dimm_attr_ddr3_st { enum spd_memory_type dram_type; enum spd_dimm_type dimm_type; u16 cas_supported; /* Flags extracted from SPD */ - dimm_flags_t flags; + union dimm_flags_ddr3_st flags; /* SDRAM width */ u8 width; /* Number of ranks */ @@ -161,7 +161,7 @@ u8 part_number[17]; /* Serial number */ u8 serial[SPD_DIMM_SERIAL_LEN]; -} dimm_attr; +}; enum ddr3_xmp_profile { DDR3_XMP_PROFILE_1 = 0, @@ -172,15 +172,15 @@ u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type type); -void dram_print_spd_ddr3(const dimm_attr *dimm); -int spd_xmp_decode_ddr3(dimm_attr *dimm, +void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); +int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, - const dimm_attr *info); + const struct dimm_attr_ddr3_st *info); /** * \brief Read double word from specified address * diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 47cd7de..92a0b72 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -174,7 +174,7 @@ spd_slot = 2 * channel + slot; printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot); - dimm_attr *const dimm = &ctrl->info.dimm[channel][slot]; + struct dimm_attr_ddr3_st *const dimm = &ctrl->info.dimm[channel][slot]; /* Search for XMP profile */ spd_xmp_decode_ddr3(dimm, spd[spd_slot], diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d6a8aa5..687386d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -66,7 +66,7 @@ FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { - const dimm_attr *dimm = &dimms->dimm[channel][slot]; + const struct dimm_attr_ddr3_st *dimm = &dimms->dimm[channel][slot]; if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) continue; @@ -245,7 +245,7 @@ dimm_info *info = &ctrl->info; FOR_ALL_CHANNELS { - dimm_attr *dimmA, *dimmB; + struct dimm_attr_ddr3_st *dimmA, *dimmB; u32 reg = 0; if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index b93902a..1622259 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -322,7 +322,7 @@ /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ typedef struct dimm_info_st { - dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; + struct dimm_attr_ddr3_st dimm[NUM_CHANNELS][NUM_SLOTS]; } dimm_info; /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 8ff0ffc..c780071 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -351,7 +351,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, struct abs_timings *saved_timings, struct sysinfo *s) { - struct dimm_attr_st decoded_dimm; + struct dimm_attr_ddr3_st decoded_dimm; if (spd_decode_ddr3(&decoded_dimm, raw_spd) != SPD_STATUS_OK) return CB_ERR; diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index f62c998..79614af 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -55,7 +55,7 @@ static void populate_smbios_tables(void *dram_data, int speed, int num_channels) { - dimm_attr dimm; + struct dimm_attr_ddr3_st dimm; enum spd_status status; /* Decode into dimm_attr struct */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a Gerrit-Change-Number: 51895 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Nico Huber, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52100 ) Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52100/comment/b7339ff7_5b40050c PS1, Line 13: . > "... for the remaining platforms. […] Done. I've specified that I only updated platforms with the InternalGfx UPD. -- To view, visit https://review.coreboot.org/c/coreboot/+/52100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Gerrit-Change-Number: 52100 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 13:00:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Michał Żygowski, Michael Niewöhner, Patrick Rudolph, Piotr Król. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52101 ) Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/skylake/systemagent.c: https://review.coreboot.org/c/coreboot/+/52101/comment/939eded6_f91eab13 PS1, Line 42: const struct soc_intel_skylake_config *const config = config_of(dev); > orphaned woups -- To view, visit https://review.coreboot.org/c/coreboot/+/52101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Gerrit-Change-Number: 52101 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 12:59:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Michał Żygowski, Patrick Rudolph, Piotr Król. Hello build bot (Jenkins), Michał Żygowski, Michael Niewöhner, Patrick Rudolph, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52101 to look at the new patch set (#2). Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option ...................................................................... soc/intel/skylake: Drop unnecessary `ignore_vtd` option It is zero for all mainboards. If one really wanted to ignore VT-d support, a user-visible Kconfig option would be a better approach. Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/protectli/vault_kbl/devicetree.cb M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 6 files changed, 3 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/52101/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Gerrit-Change-Number: 52101 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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