April 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/amd/common: Add ESPI_DEBUG_PRINT macro & Kconfig option
by Martin Roth (Code Review) April 5, 2021

April 5, 2021

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51750 ) Change subject: soc/amd/common: Add ESPI_DEBUG_PRINT macro & Kconfig option ...................................................................... Abandoned Meh -- To view, visit https://review.coreboot.org/c/coreboot/+/51750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbd76f283e37ea3acbaf68735dc1bcbd13ddab8b Gerrit-Change-Number: 51750 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common: Add some ESPI register definitions
by Martin Roth (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51747 ) Change subject: soc/amd/common: Add some ESPI register definitions ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/include/amdblocks/espi.h: https://review.coreboot.org/c/coreboot/+/51747/comment/d89ecc31_1fe27858 PS6, Line 20: #define ESPI_IO_BASE_OFFSET_REG1 0x48 > No, they're not required, but it seems useful to have them. Ack. -- To view, visit https://review.coreboot.org/c/coreboot/+/51747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Gerrit-Change-Number: 51747 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Apr 2021 17:14:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Add some ESPI register definitions
by Martin Roth (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51747 ) Change subject: soc/amd/common: Add some ESPI register definitions ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/block/include/amdblocks/espi.h: https://review.coreboot.org/c/coreboot/+/51747/comment/799ceab0_4017ea51 PS6, Line 20: #define ESPI_IO_BASE_OFFSET_REG1 0x48 > Do we need the _REG1,_REG2,_REG3? I don't see them being used as long as we have the ESPI_IO_RANGE_B […] No, they're not required, but it seems useful to have them. -- To view, visit https://review.coreboot.org/c/coreboot/+/51747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Gerrit-Change-Number: 51747 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Apr 2021 17:14:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update GPIO configuration
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Martin Roth, Furquan Shaikh, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51675 ) Change subject: mb/google/guybrush: Update GPIO configuration ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Gerrit-Change-Number: 51675 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Apr 2021 17:14:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update GPIO configuration
by Martin Roth (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Furquan Shaikh, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51675 ) Change subject: mb/google/guybrush: Update GPIO configuration ...................................................................... Patch Set 11: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51675/comment/5adfce04_17db3e65 PS10, Line 9: Init I2C3 early for GSC communication. > This isn't done as part of this CL. Done File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/51675/comment/cf09620e_733a7a04 PS10, Line 59: // PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), > I think it's best not to leave commented out code here. […] Done https://review.coreboot.org/c/coreboot/+/51675/comment/f084ea59_6f706890 PS10, Line 180: SPI_CLK2 > nit: Probably name this ESPI_SOC_CLK? That will make it clear that this is related to eSPI clock. Done, here and above. -- To view, visit https://review.coreboot.org/c/coreboot/+/51675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Gerrit-Change-Number: 51675 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 05 Apr 2021 17:12:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update GPIO configuration
by Martin Roth (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Martin Roth, Felix Held. Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51675 to look at the new patch set (#11). Change subject: mb/google/guybrush: Update GPIO configuration ...................................................................... mb/google/guybrush: Update GPIO configuration Initialize all eSPI signals including PCIE_RST0_L early for EC communication. - Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is a temporary workaround until PCIE_RST_L comes up on its own. - Make sure all GPIO muxes initialized early are re-initialized. BUG=b:183340503 TEST=Boot Guybrush Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/51675/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/51675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e Gerrit-Change-Number: 51675 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Mathew King <mathewk(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Add ACPI support for Chrome EC
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51628 ) Change subject: mb/google/mancomb: Add ACPI support for Chrome EC ...................................................................... mb/google/mancomb: Add ACPI support for Chrome EC BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51628 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/dsdt.asl M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 2 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/dsdt.asl b/src/mainboard/google/mancomb/dsdt.asl index 7b8982a..73a2ea5 100644 --- a/src/mainboard/google/mancomb/dsdt.asl +++ b/src/mainboard/google/mancomb/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <variant/ec.h> + DefinitionBlock ( "dsdt.aml", "DSDT", @@ -13,4 +15,13 @@ #include <acpi/dsdt_top.asl> #include <soc.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } } diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index db21dd4..c4ef3f5 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -42,5 +42,10 @@ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) end + device ref lpc_bridge on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end end # domain end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/51628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibce15d2e4340515353a33c593d065df50a15286a Gerrit-Change-Number: 51628 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Enable eSPI VW SCI events
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51627 ) Change subject: mb/google/mancomb: Enable eSPI VW SCI events ...................................................................... mb/google/mancomb: Enable eSPI VW SCI events Mancomb does not have a dedicated SCI pin so it uses VW. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/ec.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/ec.c b/src/mainboard/google/mancomb/ec.c index 1794acf..f89bc9e 100644 --- a/src/mainboard/google/mancomb/ec.c +++ b/src/mainboard/google/mancomb/ec.c @@ -4,8 +4,18 @@ #include <amdblocks/gpio_banks.h> #include <amdblocks/smi.h> #include <ec/google/chromeec/ec.h> +#include <soc/smi.h> #include <variant/ec.h> +static const struct sci_source espi_sci_sources[] = { + { + .scimap = SMITYPE_ESPI_SYS, + .gpe = GEVENT_24, + .direction = SMI_SCI_LVL, + .level = SMI_SCI_LVL_HIGH + } +}; + void mainboard_ec_init(void) { const struct google_chromeec_event_info info = { @@ -17,4 +27,7 @@ }; google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + + /* Configure eSPI VW SCI events */ + gpe_configure_sci(espi_sci_sources, ARRAY_SIZE(espi_sci_sources)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001 Gerrit-Change-Number: 51627 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Enable Chrome EC SKUID and BOARDID
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51626 ) Change subject: mb/google/mancomb: Enable Chrome EC SKUID and BOARDID ...................................................................... mb/google/mancomb: Enable Chrome EC SKUID and BOARDID BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/51626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 3fb60d4..ba8f1d4 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -10,7 +10,9 @@ select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_SKUID select ELOG select ELOG_GSMI select HAVE_ACPI_RESUME -- To view, visit https://review.coreboot.org/c/coreboot/+/51626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70283c8d93b5cbabdaf5a8ab947d5f8444940dff Gerrit-Change-Number: 51626 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Add smihandler
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51625 ) Change subject: mb/google/mancomb: Add smihandler ...................................................................... mb/google/mancomb: Add smihandler BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/51625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/Kconfig A src/mainboard/google/mancomb/smihandler.c M src/mainboard/google/mancomb/variants/baseboard/Makefile.inc M src/mainboard/google/mancomb/variants/baseboard/gpio.c M src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h 5 files changed, 53 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index fd59874..3fb60d4 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -11,6 +11,8 @@ select BOARD_ROMSIZE_KB_16384 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI + select ELOG + select ELOG_GSMI select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select SOC_AMD_CEZANNE diff --git a/src/mainboard/google/mancomb/smihandler.c b/src/mainboard/google/mancomb/smihandler.c new file mode 100644 index 0000000..6facb76 --- /dev/null +++ b/src/mainboard/google/mancomb/smihandler.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/smm.h> +#include <elog.h> +#include <variant/ec.h> + +void mainboard_smi_gpi(u32 gpi_sts) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + + gpios = variant_sleep_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} diff --git a/src/mainboard/google/mancomb/variants/baseboard/Makefile.inc b/src/mainboard/google/mancomb/variants/baseboard/Makefile.inc index e8a05db..3b86b93 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/mancomb/variants/baseboard/Makefile.inc @@ -3,3 +3,5 @@ ramstage-y += gpio.c verstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index effa3f2..5a6f2ac 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -168,6 +168,11 @@ PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), }; +/* GPIO configuration for sleep */ +static const struct soc_amd_gpio sleep_gpio_table[] = { + /* TODO: Fill sleep gpio configuration */ +}; + const struct soc_amd_gpio *__weak variant_base_gpio_table(size_t *size) { *size = ARRAY_SIZE(base_gpio_table); @@ -183,3 +188,8 @@ *size = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +} diff --git a/src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h index 677d4d7..dccaed0 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/mancomb/variants/baseboard/include/baseboard/variants.h @@ -21,4 +21,7 @@ /* This function provides early GPIO init in bootblock or psp. */ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +/* This function provides GPIO settings before entering sleep. */ +const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); + #endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/51625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52411917d9e7e8f8d9ac5d1c9b426a58ba09f5ae Gerrit-Change-Number: 51625 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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