coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede: add lalala variant
by Aaron Durbin (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Martin Roth, Paul Menzel, Angel Pons. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52031 ) Change subject: mb/google/dedede: add lalala variant ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/dedede/variants/lalala/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52031/comment/5ac8acd2_80f355bb PS2, Line 11: TBD > Hm? This was lifted from magalor. https://review.coreboot.org/c/coreboot/+/52031/comment/ed4977d0_6e5690d5 PS2, Line 300: device pci 1c.7 on > nit: I'd move this device up, so that the dev. […] I was following magolor. I think we can reorder everything in a separate change. -- To view, visit https://review.coreboot.org/c/coreboot/+/52031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Gerrit-Change-Number: 52031 Gerrit-PatchSet: 2 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:30:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Tim Wawrzynczak (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Arthur Heymans, Michael Niewöhner, Aaron Durbin, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/52093/comment/87746767_50b58aa8 PS1, Line 77: : if (base == 0) : return; : > Yeah, but the message is still far away from what the code does. […] +1 to a different message for `base == 0` -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
by Tim Wawrzynczak (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 ) Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/51159/comment/dedc4340_80c59c0b PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ > You are correct, this recommendation comes from the BWG guides IIRC. […] for posterity: Sorry I misunderstood what you were getting at, we talked on IRC, I realized the error of my ways and trying a new patchset. we also realized the old IDENTITY constraint appears to be required for PCIe RPs, -- To view, visit https://review.coreboot.org/c/coreboot/+/51159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Gerrit-Change-Number: 51159 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:19:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2
by Tim Wawrzynczak (Code Review) 05 Apr '21

05 Apr '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52088 ) Change subject: mb/google/brya: Enable south XHCI ports 1 and 2 ...................................................................... mb/google/brya: Enable south XHCI ports 1 and 2 FSP v2081 has a bug where it uses the information about south XHCI ports to enable TCSS XHCI ports. This change works around this bug by enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0 already enables south XHCI port 1 in overridetree.cb, however, it is still enabled in baseboard/devicetree in case more variants are added to brya before FSP is fixed. BUG=b:184324979 TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled. Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 3155d04..d7e2522 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -39,6 +39,12 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 + # uses port enable for south XHCI ports to determine if TCSS + # ports should be enabled. Until FSP is fixed, enable south + # XHCI ports 1 and 2. + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "SerialIoI2cMode" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/52088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Gerrit-Change-Number: 52088 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2
by Tim Wawrzynczak (Code Review) 05 Apr '21

05 Apr '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Ronak Kanabar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52088 ) Change subject: mb/google/brya: Enable south XHCI ports 1 and 2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Gerrit-Change-Number: 52088 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:15:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... nb/intel/sandybridge: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/stout/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_common.c 8 files changed, 3 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 5461b15..73dce98 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -33,8 +33,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 18ed380..2627fae 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0x0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b4d3800..5f1ea6b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21f9 inherit diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index de91bba..e0557ca 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0f3ee5c..6cda62b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -31,8 +31,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on ioapic_irq 4 INTA 0x10 ioapic_irq 4 INTB 0x11 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 20c994e..6f49cfe 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 824af3e..99d9763 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -43,11 +43,6 @@ struct i915_gpu_controller_info gfx; - /* - * Maximum PCI MMIO size in MiB. - */ - u16 pci_mmio_size; - /* Data for RAM init */ /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 72621e3..c7273ad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -338,24 +338,6 @@ } } -#define DEFAULT_PCI_MMIO_SIZE 2048 - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} - /* * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. * The ME/PCU/.. has the ability to change this. @@ -382,6 +364,8 @@ return !(reg32 & (1 << 25)); } +#define DEFAULT_PCI_MMIO_SIZE 2048 + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; @@ -389,7 +373,7 @@ size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; - mmiosize = get_mmio_size(); + mmiosize = DEFAULT_PCI_MMIO_SIZE; ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sandybridge boards: Drop default `pci_mmio_size`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52071 ) Change subject: sandybridge boards: Drop default `pci_mmio_size` ...................................................................... sandybridge boards: Drop default `pci_mmio_size` 2 GiB is the default already. Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/asus/p8z77-v_lx2/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 16 files changed, 0 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 5050758..ee192cf 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 7b90149..22b474d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index eddca81..73671ee 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 969169c..60e54ae 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 0fc6dc1..40f8e6d 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1043 0x84ca inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 118a58e..9dc6a7c 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 0c24a9d..d753411 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1458 0x5000 inherit device pci 00.0 on # Host bridge diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index d0ec09c..479d813 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index fbff203..db902be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 61535df..f1ec5e7 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index ffd1d24..441abf2b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4b956757..6b7c6a2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index d9ececa..925bfb9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21fb inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 296be73..48d5791 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 7adc0f5..23744e1 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21f6 inherit diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 3f1934d..de0c9a2 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21db inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/52071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Gerrit-Change-Number: 52071 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/raminit.c 5 files changed, 1 insertion(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index af770dc..5f167df 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543d..e142a1c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b57b3fe..d5f96cb 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bc..ab589ea 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073dda..34e5657 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096) -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: device/dram/ddr3: Drop unused MRS helpers
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47343 ) Change subject: device/dram/ddr3: Drop unused MRS helpers ...................................................................... device/dram/ddr3: Drop unused MRS helpers These aren't used anywhere anymore. Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/dram/ddr3.c M src/include/device/dram/ddr3.h 2 files changed, 0 insertions(+), 353 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47343/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index ab6d828..16a76a2 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -638,226 +638,3 @@ printk(BIOS_INFO, " tCMDmin : %3u\n", DIV_ROUND_UP(dimm->tCMD, 256)); } - -/*============================================================================== - *= DDR3 MRS helpers - *----------------------------------------------------------------------------*/ - -/* - * MRS command structure: - * cmd[15:0] = Address pins MA[15:0] - * cmd[18:16] = Bank address BA[2:0] - */ - -/* Map tWR value to a bitmask of the MR0 cycle */ -static u16 ddr3_twr_to_mr0_map(u8 twr) -{ - if ((twr >= 5) && (twr <= 8)) - return (twr - 4) << 9; - - /* - * From 8T onwards, we can only use even values. Round up if we are - * given an odd value. - */ - if ((twr >= 9) && (twr <= 14)) - return ((twr + 1) >> 1) << 9; - - /* tWR == 16T is [000] */ - return 0; -} - -/* Map the CAS latency to a bitmask for the MR0 cycle */ -static u16 ddr3_cas_to_mr0_map(u8 cas) -{ - u16 mask = 0; - /* A[6:4] are bits [2:0] of (CAS - 4) */ - mask = ((cas - 4) & 0x07) << 4; - - /* A2 is the MSB of (CAS - 4) */ - if ((cas - 4) & (1 << 3)) - mask |= (1 << 2); - - return mask; -} - -/** - * \brief Get command address for a DDR3 MR0 command - * - * The DDR3 specification only covers odd write_recovery up to 7T. If an odd - * write_recovery greater than 7 is specified, it will be rounded up. If a tWR - * greater than 8 is specified, it is recommended to explicitly round it up or - * down before calling this function. - * - * write_recovery and cas are given in clock cycles. For example, a CAS of 7T - * should be given as 7. - * - * @param precharge_pd - * @param write_recovery Write recovery latency, tWR in clock cycles. - * @param dll_reset - * @param mode - * @param cas CAS latency in clock cycles. - * @param burst_type - * @param burst_length - */ -mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type burst_type, - enum ddr3_mr0_burst_length burst_length) -{ - mrs_cmd_t cmd = 0 << 16; - - if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) - cmd |= (1 << 12); - - cmd |= ddr3_twr_to_mr0_map(write_recovery); - - if (dll_reset == DDR3_MR0_DLL_RESET_YES) - cmd |= (1 << 8); - - if (mode == DDR3_MR0_MODE_TEST) - cmd |= (1 << 7); - - cmd |= ddr3_cas_to_mr0_map(cas); - - if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) - cmd |= (1 << 3); - - cmd |= (burst_length & 0x03) << 0; - - return cmd; -} - -static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) -{ - u16 mask = 0; - /* A9 <-> rtt_nom[2] */ - if (rtt_nom & (1 << 2)) - mask |= (1 << 9); - /* A6 <-> rtt_nom[1] */ - if (rtt_nom & (1 << 1)) - mask |= (1 << 6); - /* A2 <-> rtt_nom[0] */ - if (rtt_nom & (1 << 0)) - mask |= (1 << 2); - - return mask; -} - -static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) -{ - u16 mask = 0; - /* A5 <-> ods[1] */ - if (ods & (1 << 1)) - mask |= (1 << 5); - /* A1 <-> ods[0] */ - if (ods & (1 << 0)) - mask |= (1 << 1); - - return mask; -} - -/** - * \brief Get command address for a DDR3 MR1 command - */ -mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods ods, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable) -{ - mrs_cmd_t cmd = 1 << 16; - - if (qoff == DDR3_MR1_QOFF_DISABLE) - cmd |= (1 << 12); - - if (tqds == DDR3_MR1_TQDS_ENABLE) - cmd |= (1 << 11); - - cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); - - if (write_leveling == DDR3_MR1_WRLVL_ENABLE) - cmd |= (1 << 7); - - cmd |= ddr3_ods_to_mr1_map(ods); - - cmd |= (additive_latency & 0x03) << 3; - - if (dll_disable == DDR3_MR1_DLL_DISABLE) - cmd |= (1 << 0); - - return cmd; -} - -/** - * \brief Get command address for a DDR3 MR2 command - * - * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be - * given as 7. - * - * @param rtt_wr - * @param extended_temp - * @param self_refresh - * @param cas_cwl CAS write latency in clock cycles. - */ - -mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl) -{ - mrs_cmd_t cmd = 2 << 16; - - cmd |= (rtt_wr & 0x03) << 9; - - if (extended_temp == DDR3_MR2_SRT_EXTENDED) - cmd |= (1 << 7); - - if (self_refresh == DDR3_MR2_ASR_AUTO) - cmd |= (1 << 6); - - cmd |= ((cas_cwl - 5) & 0x07) << 3; - - return cmd; -} - -/** - * \brief Get command address for a DDR3 MR3 command - * - * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read - * leveling mode. Zero for normal operation. - */ -mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) -{ - mrs_cmd_t cmd = 3 << 16; - - if (dataflow_from_mpr) - cmd |= (1 << 2); - - return cmd; -} - -/** - * \brief Mirror the address bits for this MRS command - * - * Swap the following bits in the MRS command: - * - MA3 <-> MA4 - * - MA5 <-> MA6 - * - MA7 <-> MA8 - * - BA0 <-> BA1 - */ -mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) -{ - u32 downshift, upshift; - /* High bits= A4 | A6 | A8 | BA1 */ - /* Low bits = A3 | A5 | A7 | BA0 */ - u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); - downshift = (cmd & (lowbits << 1)); - upshift = (cmd & lowbits); - cmd &= ~(lowbits | (lowbits << 1)); - cmd |= (downshift >> 1) | (upshift << 1); - return cmd; -} diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0814990..4a5134f 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -181,135 +181,5 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, const dimm_attr *info); -/** - * \brief Read double word from specified address - * - * Should be useful when doing an MRS to the DIMM - */ -static inline u32 volatile_read(volatile uintptr_t addr) -{ - volatile u32 result; - result = *(volatile u32 *)addr; - return result; -} - -/** - * \brief Representation of an MRS command - * - * This represents an MRS command as seen by the DIMM. This is not a memory - * address that can be read to generate an MRS command. The mapping of CPU - * to memory pins is hardware-dependent. - * \n - * The idea is to generalize the MRS code, and only need a hardware-specific - * function to map the MRS bits to CPU address bits. An MRS command can be - * sent like: - * @code{.c} - * u32 addr; - * mrs_cmd_t mrs; - * chipset_enable_mrs_command_mode(); - * mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl) - * if (rank_has_mirrorred_pins) - * mrs = ddr3_mrs_mirror_pins(mrs); - * addr = chipset_specific_get_mrs_addr(mrs); - * volatile_read(addr); - * @endcode - * - * The MRS representation has the following structure: - * - cmd[15:0] = Address pins MA[15:0] - * - cmd[18:16] = Bank address BA[2:0] - */ -typedef u32 mrs_cmd_t; - -enum ddr3_mr0_precharge { - DDR3_MR0_PRECHARGE_SLOW = 0, - DDR3_MR0_PRECHARGE_FAST = 1, -}; -enum ddr3_mr0_mode { - DDR3_MR0_MODE_NORMAL = 0, - DDR3_MR0_MODE_TEST = 1, -}; -enum ddr3_mr0_dll_reset { - DDR3_MR0_DLL_RESET_NO = 0, - DDR3_MR0_DLL_RESET_YES = 1, -}; -enum ddr3_mr0_burst_type { - DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, - DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, -}; -enum ddr3_mr0_burst_length { - DDR3_MR0_BURST_LENGTH_8 = 0, - DDR3_MR0_BURST_LENGTH_CHOP = 1, - DDR3_MR0_BURST_LENGTH_4 = 2, -}; -mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type interleaved_burst, - enum ddr3_mr0_burst_length burst_length); - -enum ddr3_mr1_qoff { - DDR3_MR1_QOFF_ENABLE = 0, - DDR3_MR1_QOFF_DISABLE = 1, -}; -enum ddr3_mr1_tqds { - DDR3_MR1_TQDS_DISABLE = 0, - DDR3_MR1_TQDS_ENABLE = 1, -}; -enum ddr3_mr1_write_leveling { - DDR3_MR1_WRLVL_DISABLE = 0, - DDR3_MR1_WRLVL_ENABLE = 1, -}; -enum ddr3_mr1_rtt_nom { - DDR3_MR1_RTT_NOM_OFF = 0, - DDR3_MR1_RTT_NOM_RZQ4 = 1, - DDR3_MR1_RTT_NOM_RZQ2 = 2, - DDR3_MR1_RTT_NOM_RZQ6 = 3, - DDR3_MR1_RTT_NOM_RZQ12 = 4, - DDR3_MR1_RTT_NOM_RZQ8 = 5, -}; -enum ddr3_mr1_additive_latency { - DDR3_MR1_AL_DISABLE = 0, - DDR3_MR1_AL_CL_MINUS_1 = 1, - DDR3_MR1_AL_CL_MINUS_2 = 2, -}; -enum ddr3_mr1_ods { - DDR3_MR1_ODS_RZQ6 = 0, - DDR3_MR1_ODS_RZQ7 = 1, -}; -enum ddr3_mr1_dll { - DDR3_MR1_DLL_ENABLE = 0, - DDR3_MR1_DLL_DISABLE = 1, -}; - -mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods output_drive_strenght, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable); - -enum ddr3_mr2_rttwr { - DDR3_MR2_RTTWR_OFF = 0, - DDR3_MR2_RTTWR_RZQ4 = 1, - DDR3_MR2_RTTWR_RZQ2 = 2, -}; -enum ddr3_mr2_srt_range { - DDR3_MR2_SRT_NORMAL = 0, - DDR3_MR2_SRT_EXTENDED = 1, -}; -enum ddr3_mr2_asr { - DDR3_MR2_ASR_MANUAL = 0, - DDR3_MR2_ASR_AUTO = 1, -}; - -mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl); - -mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); -mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); #endif /* DEVICE_DRAM_DDR3L_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf2fc0d07a772886e90fba4f66591a7b0a40e6c Gerrit-Change-Number: 47343 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: nb/intel/sandybridge: Rename `pdwm_mode` enum
by Angel Pons (Code Review) 05 Apr '21

05 Apr '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51901 ) Change subject: nb/intel/sandybridge: Rename `pdwm_mode` enum ...................................................................... nb/intel/sandybridge: Rename `pdwm_mode` enum The `pdwm` part was supposed to be an abbreviation of `power down`, but it is neither self-explanatory nor properly-spelled. Rename the enum. Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 687386d..72621e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -684,7 +684,7 @@ } /* Obtain optimal power down mode for current configuration */ -static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) { if (ctrl->tXP > 8) return PDM_NONE; @@ -703,7 +703,7 @@ u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum pdwm_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 1622259..c24b3a0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -306,7 +306,7 @@ */ #define MRC_CACHE_VERSION 5 -enum pdwm_mode { +enum power_down_mode { PDM_NONE = 0, PDM_APD = 1, PDM_PPD = 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/51901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874 Gerrit-Change-Number: 51901 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021