April 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: mb/google/dedede: add lalala variant
by Aaron Durbin (Code Review) April 5, 2021

April 5, 2021

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52031 ) Change subject: mb/google/dedede: add lalala variant ...................................................................... mb/google/dedede: add lalala variant The Lalala variant is a design that differs only in replacing Cr50 with a discrete TPM part. BUG=b:184151664 Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52031 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/lalala/Makefile.inc A src/mainboard/google/dedede/variants/lalala/include/variant/ec.h A src/mainboard/google/dedede/variants/lalala/include/variant/gpio.h A src/mainboard/google/dedede/variants/lalala/memory/Makefile.inc A src/mainboard/google/dedede/variants/lalala/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/lalala/memory/mem_list_variant.txt A src/mainboard/google/dedede/variants/lalala/overridetree.cb A src/mainboard/google/dedede/variants/lalala/variant.c 10 files changed, 369 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Aseda Aboagye: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 66541b6..1190e969 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -98,6 +98,7 @@ default "Waddledoo" if BOARD_GOOGLE_WADDLEDOO default "Waddledee" if BOARD_GOOGLE_WADDLEDEE default "Wheelie" if BOARD_GOOGLE_WHEELIE + default "Lalala" if BOARD_GOOGLE_LALALA default "Magolor" if BOARD_GOOGLE_MAGOLOR default "Metaknight" if BOARD_GOOGLE_METAKNIGHT default "Lantis" if BOARD_GOOGLE_LANTIS @@ -132,6 +133,7 @@ default "waddledoo" if BOARD_GOOGLE_WADDLEDOO default "waddledee" if BOARD_GOOGLE_WADDLEDEE default "wheelie" if BOARD_GOOGLE_WHEELIE + default "lalala" if BOARD_GOOGLE_LALALA default "magolor" if BOARD_GOOGLE_MAGOLOR default "metaknight" if BOARD_GOOGLE_METAKNIGHT default "lantis" if BOARD_GOOGLE_LANTIS diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 5b6a41f..de3a0bd 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -62,6 +62,14 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP +config BOARD_GOOGLE_LALALA + bool "-> Lalala" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_INTEL_MIPI_CAMERA + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select SOC_INTEL_COMMON_BLOCK_IPU + config BOARD_GOOGLE_MAGOLOR bool "-> Magolor" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 diff --git a/src/mainboard/google/dedede/variants/lalala/Makefile.inc b/src/mainboard/google/dedede/variants/lalala/Makefile.inc new file mode 100644 index 0000000..24c75d1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/dedede/variants/lalala/include/variant/ec.h b/src/mainboard/google/dedede/variants/lalala/include/variant/ec.h new file mode 100644 index 0000000..27c930d --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/include/variant/ec.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +/* Enable Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/dedede/variants/lalala/include/variant/gpio.h b/src/mainboard/google/dedede/variants/lalala/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/lalala/memory/Makefile.inc b/src/mainboard/google/dedede/variants/lalala/memory/Makefile.inc new file mode 100644 index 0000000..285df73 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lalala/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/lalala/memory/dram_id.generated.txt new file mode 100644 index 0000000..100c322 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/lalala/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/lalala/memory/mem_list_variant.txt new file mode 100644 index 0000000..f05a5af --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/lalala/overridetree.cb b/src/mainboard/google/dedede/variants/lalala/overridetree.cb new file mode 100644 index 0000000..5f83e4f --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/overridetree.cb @@ -0,0 +1,307 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | TBD | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #| I2C5 | TBD | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + }" + + register "power_limits_config" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "tcc_offset" = "15" # TCC of 90C + + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000)}" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)}" + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 7000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 12000, + .max_power = 12000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 3000 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # SA Thermal device + device pci 05.0 on # IPU - MIPI Camera + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "1" + register "cio2_lanes_used" = "{2}" + register "cio2_lane_endpoint[0]" = ""^I2C3.CAM0"" + register "cio2_prt[0]" = "2" + device generic 0 on end + end + end + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.wake" = "GPE0_DW0_03" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end # I2C 0 + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "reset_delay_ms" = "100" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + end # I2C 2 + device pci 15.3 on # I2C 3 + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2 + register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF DAC"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""GT24C08"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "pr0" = ""\\_SB.PCI0.I2C3.CAM0.PRIC"" + + register "nvm_size" = "0x2000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c08"" + + device i2c 50 on end + end + end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1e.2 off end # GSPI 0 + device pci 1f.3 on end # Intel HDA + device pci 1f.5 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end # Discrete TPM + end # chip drivers/pc80/tpm + end # PCH SPI + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + end +end diff --git a/src/mainboard/google/dedede/variants/lalala/variant.c b/src/mainboard/google/dedede/variants/lalala/variant.c new file mode 100644 index 0000000..8bbae62 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lalala/variant.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + if (fw_config_probe(FW_CONFIG(TABLETMODE, TABLETMODE_ENABLED))) + return "wifi_sar-lalala.hex"; + + return WIFI_SAR_CBFS_DEFAULT_FILENAME; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Gerrit-Change-Number: 52031 Gerrit-PatchSet: 3 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: add discrete TPM 2.0 configuration
by Aaron Durbin (Code Review) April 5, 2021

April 5, 2021

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52030 ) Change subject: mb/google/dedede: add discrete TPM 2.0 configuration ...................................................................... mb/google/dedede: add discrete TPM 2.0 configuration There are forthcoming designs that will be utilizing a discrete TPM 2.0 solution. Split the existing dedede configuration options so future mainboard variants can easily select the appropriate Kconfig option using the newly introduced options: - BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 - BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 The existing variants all select the former option, BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those designs currently utilize Cr50. BUG=b:184151664 Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aseda Aboagye <aaboagye(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/baseboard/gpio.c 4 files changed, 62 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Aseda Aboagye: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9f19dea..66541b6 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,7 +1,6 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 - select CR50_USE_LONG_INTERRUPT_PULSES select DPTF_USE_EISA_HID select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC @@ -22,7 +21,6 @@ select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT @@ -32,6 +30,17 @@ select SOC_INTEL_COMMON_BLOCK_IPU select DRIVERS_GENERIC_ALC1015 +config BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + def_bool n + select CR50_USE_LONG_INTERRUPT_PULSES + select MAINBOARD_HAS_SPI_TPM_CR50 + select BOARD_GOOGLE_BASEBOARD_DEDEDE + +config BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + def_bool n + select MAINBOARD_HAS_LPC_TPM + select BOARD_GOOGLE_BASEBOARD_DEDEDE + if BOARD_GOOGLE_BASEBOARD_DEDEDE config BASEBOARD_DEDEDE_LAPTOP @@ -39,7 +48,7 @@ select SYSTEM_TYPE_LAPTOP config CHROMEOS - select CHROMEOS_CSE_BOARD_RESET_OVERRIDE + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON @@ -65,9 +74,6 @@ int default 512 -config DRIVER_TPM_SPI_BUS - default 0x1 - config FMDFILE string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 @@ -111,10 +117,6 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_DEDEDE -config TPM_TIS_ACPI_INTERRUPT - int - default 4 # GPE0_DW0_4 (GPP_B4) - config UART_FOR_CONSOLE int default 2 @@ -142,3 +144,22 @@ default "cret" if BOARD_GOOGLE_CRET endif #BOARD_GOOGLE_BASEBOARD_DEDEDE + +if BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + +config DRIVER_TPM_SPI_BUS + default 0x1 + +config TPM_TIS_ACPI_INTERRUPT + int + default 4 # GPE0_DW0_4 (GPP_B4) + +endif #BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + +if BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + +config TPM_PIRQ + hex + default 0x24 # GPP_B4_IRQ + +endif #BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 0361e85..5b6a41f 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -1,24 +1,24 @@ config BOARD_GOOGLE_BOTEN bool "Boten" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_BOTEN_LEGACY bool "Boten (Legacy)" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_DEDEDE bool "Dedede" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_DRAWCIA bool "Drawcia" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -27,7 +27,7 @@ config BOARD_GOOGLE_DRAWCIA_LEGACY bool "Drawcia (Legacy)" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A @@ -36,14 +36,14 @@ config BOARD_GOOGLE_MADOO bool "-> Madoo" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_WADDLEDOO bool "Waddledoo" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_MAX98357A @@ -53,18 +53,18 @@ config BOARD_GOOGLE_WADDLEDEE bool "Waddledee" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 config BOARD_GOOGLE_WHEELIE bool "Wheelie" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP config BOARD_GOOGLE_MAGOLOR bool "-> Magolor" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR @@ -72,24 +72,24 @@ config BOARD_GOOGLE_METAKNIGHT bool "-> Metaknight" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP config BOARD_GOOGLE_LANTIS bool "-> Lantis" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_GALTIC bool "-> Galtic" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_SASUKE bool "-> Sasuke" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 @@ -97,30 +97,30 @@ config BOARD_GOOGLE_STORO bool "-> Storo" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_SASUKETTE bool "-> Sasukette" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP config BOARD_GOOGLE_KRACKO bool "-> Kracko" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_BLIPPER bool "-> Blipper" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP config BOARD_GOOGLE_CRET bool "-> Cret" - select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index fabdc5e..26afb69 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -40,7 +40,8 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); - mainboard_update_soc_chip_config(); + if (CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)) + mainboard_update_soc_chip_config(); } static void mainboard_dev_init(struct device *dev) diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index c162ac3..79bae96 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -72,6 +72,7 @@ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR/GSPI0_CS1_N */ PAD_NC(GPP_B14, NONE), +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50) /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -80,6 +81,13 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#else /* BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 */ + /* Nothing connected on GSPI1 */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), +#endif /* B19 : GSPI1_CS0_N */ PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK */ @@ -389,6 +397,7 @@ static const struct pad_config early_gpio_table[] = { /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), +#if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50) /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ @@ -397,6 +406,7 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), +#endif /* C0 : RAM_STRAP_0 */ PAD_CFG_GPI(GPP_C0, NONE, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/52030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba Gerrit-Change-Number: 52030 Gerrit-PatchSet: 3 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: add lalala variant
by Aaron Durbin (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Martin Roth, Paul Menzel, Angel Pons. Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52031 ) Change subject: mb/google/dedede: add lalala variant ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/dedede/variants/lalala/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52031/comment/5ac8acd2_80f355bb PS2, Line 11: TBD > Hm? This was lifted from magalor. https://review.coreboot.org/c/coreboot/+/52031/comment/ed4977d0_6e5690d5 PS2, Line 300: device pci 1c.7 on > nit: I'd move this device up, so that the dev. […] I was following magolor. I think we can reorder everything in a separate change. -- To view, visit https://review.coreboot.org/c/coreboot/+/52031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7abb9637cd5a13ac896396781b19feb156c948 Gerrit-Change-Number: 52031 Gerrit-PatchSet: 2 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:30:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Do not bridge I/O resources with base=0 to LPC
by Tim Wawrzynczak (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Arthur Heymans, Michael Niewöhner, Aaron Durbin, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 ) Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/52093/comment/87746767_50b58aa8 PS1, Line 77: : if (base == 0) : return; : > Yeah, but the message is still far away from what the code does. […] +1 to a different message for `base == 0` -- To view, visit https://review.coreboot.org/c/coreboot/+/52093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69468db641ad8c1bf056b6871e812196e784e515 Gerrit-Change-Number: 52093 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
by Tim Wawrzynczak (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Nico Huber, Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51159 ) Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/51159/comment/dedc4340_80c59c0b PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */ > You are correct, this recommendation comes from the BWG guides IIRC. […] for posterity: Sorry I misunderstood what you were getting at, we talked on IRC, I realized the error of my ways and trying a new patchset. we also realized the old IDENTITY constraint appears to be required for PCIe RPs, -- To view, visit https://review.coreboot.org/c/coreboot/+/51159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Gerrit-Change-Number: 51159 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:19:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2
by Tim Wawrzynczak (Code Review) April 5, 2021

April 5, 2021

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52088 ) Change subject: mb/google/brya: Enable south XHCI ports 1 and 2 ...................................................................... mb/google/brya: Enable south XHCI ports 1 and 2 FSP v2081 has a bug where it uses the information about south XHCI ports to enable TCSS XHCI ports. This change works around this bug by enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0 already enables south XHCI port 1 in overridetree.cb, however, it is still enabled in baseboard/devicetree in case more variants are added to brya before FSP is fixed. BUG=b:184324979 TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled. Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 3155d04..d7e2522 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -39,6 +39,12 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 + # uses port enable for south XHCI ports to determine if TCSS + # ports should be enabled. Until FSP is fixed, enable south + # XHCI ports 1 and 2. + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "SerialIoI2cMode" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/52088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Gerrit-Change-Number: 52088 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2
by Tim Wawrzynczak (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Furquan Shaikh, Subrata Banik, Ronak Kanabar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52088 ) Change subject: mb/google/brya: Enable south XHCI ports 1 and 2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Gerrit-Change-Number: 52088 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 05 Apr 2021 14:15:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52072 ) Change subject: nb/intel/sandybridge: Drop `pci_mmio_size` ...................................................................... nb/intel/sandybridge: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/stout/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_common.c 8 files changed, 3 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 5461b15..73dce98 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -33,8 +33,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 18ed380..2627fae 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0x0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index b4d3800..5f1ea6b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21f9 inherit diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index de91bba..e0557ca 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 0f3ee5c..6cda62b 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -31,8 +31,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on ioapic_irq 4 INTA 0x10 ioapic_irq 4 INTB 0x11 diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 20c994e..6f49cfe 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 824af3e..99d9763 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -43,11 +43,6 @@ struct i915_gpu_controller_info gfx; - /* - * Maximum PCI MMIO size in MiB. - */ - u16 pci_mmio_size; - /* Data for RAM init */ /* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 72621e3..c7273ad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -338,24 +338,6 @@ } } -#define DEFAULT_PCI_MMIO_SIZE 2048 - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} - /* * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. * The ME/PCU/.. has the ability to change this. @@ -382,6 +364,8 @@ return !(reg32 & (1 << 25)); } +#define DEFAULT_PCI_MMIO_SIZE 2048 + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; @@ -389,7 +373,7 @@ size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; uint16_t ggc; - mmiosize = get_mmio_size(); + mmiosize = DEFAULT_PCI_MMIO_SIZE; ggc = pci_read_config16(HOST_BRIDGE, GGC); if (!(ggc & 2)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/52072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Gerrit-Change-Number: 52072 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sandybridge boards: Drop default `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52071 ) Change subject: sandybridge boards: Drop default `pci_mmio_size` ...................................................................... sandybridge boards: Drop default `pci_mmio_size` 2 GiB is the default already. Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8h61-m_lx/devicetree.cb M src/mainboard/asus/p8h61-m_pro/devicetree.cb M src/mainboard/asus/p8z77-v_lx2/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb 16 files changed, 0 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 5050758..ee192cf 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 7b90149..22b474d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index eddca81..73671ee 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index 969169c..60e54ae 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0x0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 0fc6dc1..40f8e6d 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1043 0x84ca inherit device pci 00.0 on end # Host bridge diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 118a58e..9dc6a7c 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 0c24a9d..d753411 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -11,8 +11,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x1458 0x5000 inherit device pci 00.0 on # Host bridge diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index d0ec09c..479d813 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -10,7 +10,6 @@ device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index fbff203..db902be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 61535df..f1ec5e7 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -16,8 +16,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0x0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index ffd1d24..441abf2b 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 4b956757..6b7c6a2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index d9ececa..925bfb9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -26,8 +26,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21fb inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 296be73..48d5791 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 7adc0f5..23744e1 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21f6 inherit diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 3f1934d..de0c9a2 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -27,8 +27,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on subsystemid 0x17aa 0x21db inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/52071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f Gerrit-Change-Number: 52071 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/ironlake: Drop `pci_mmio_size`
by Angel Pons (Code Review) April 5, 2021

April 5, 2021

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52070 ) Change subject: nb/intel/ironlake: Drop `pci_mmio_size` ...................................................................... nb/intel/ironlake: Drop `pci_mmio_size` There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb M src/northbridge/intel/ironlake/chip.h M src/northbridge/intel/ironlake/raminit.c 5 files changed, 1 insertion(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index af770dc..5f167df 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -23,8 +23,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543d..e142a1c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b57b3fe..d5f96cb 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -24,8 +24,6 @@ end end - register "pci_mmio_size" = "2048" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1025 0x0379 diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bc..ab589ea 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073dda..34e5657 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096) -- To view, visit https://review.coreboot.org/c/coreboot/+/52070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c Gerrit-Change-Number: 52070 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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