April 2021 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/amd: Make espi_configure_decodes private
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52059 ) Change subject: soc/amd: Make espi_configure_decodes private ...................................................................... soc/amd: Make espi_configure_decodes private This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/psp_verstage/fch.c 5 files changed, 15 insertions(+), 18 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index acd2a7a..0e351a9 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -70,6 +70,5 @@ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { espi_clear_decodes(); espi_setup(); - espi_configure_decodes(); } } diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 7ca5b05..f5e7d31 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -101,12 +101,6 @@ int espi_open_mmio_window(uint32_t base, size_t size); /* - * Configure generic and standard I/O decode windows using the espi_config structure settings - * provided by mainboard in device tree. - */ -void espi_configure_decodes(void); - -/* * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing * the decodes, or if something else has previously setup decode windows that conflict * with the windows that coreboot needs. diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c7269d0..0b690b8 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -298,19 +298,22 @@ return &soc_cfg->espi_config; } -void espi_configure_decodes(void) +static int espi_configure_decodes(const struct espi_config *cfg) { - int i; - const struct espi_config *cfg = espi_get_config(); + int i, ret; espi_enable_decode(cfg->std_io_decode_bitmap); for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { if (cfg->generic_io_range[i].size == 0) continue; - espi_open_generic_io_window(cfg->generic_io_range[i].base, - cfg->generic_io_range[i].size); + ret = espi_open_generic_io_window(cfg->generic_io_range[i].base, + cfg->generic_io_range[i].size); + if (ret) + return ret; } + + return 0; } #define ESPI_DN_TX_HDR0 0x00 @@ -966,6 +969,11 @@ return -1; } + if (espi_configure_decodes(cfg) == -1) { + printk(BIOS_ERR, "Error: Configuring decodes failed!\n"); + return -1; + } + /* Enable subtractive decode if configured */ espi_setup_subtractive_decode(cfg); diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index 63e192f..5f47638 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -77,8 +77,6 @@ if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) lpc_disable_spi_rom_sharing(); - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) espi_setup(); - espi_configure_decodes(); - } } diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index e6c70f6..a032bde 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -153,8 +153,6 @@ void verstage_soc_init(void) { - if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { + if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) espi_setup(); - espi_configure_decodes(); - } } -- To view, visit https://review.coreboot.org/c/coreboot/+/52059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Gerrit-Change-Number: 52059 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by build bot (Jenkins) (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Ronak Kanabar, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51849 ) Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... Patch Set 6: (2 comments) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/51849/comment/fae1d14c_49450aff PS6, Line 205: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/51849/comment/a226fb77_f3240b7e PS6, Line 214: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Apr 2021 16:37:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable VT-d
by Meera Ravindranath (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Ronak Kanabar, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Subrata Banik, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51849 to look at the new patch set (#6). Change subject: soc/intel/alderlake: Enable VT-d ...................................................................... soc/intel/alderlake: Enable VT-d Update UPDs required for enabling VT-d. TEST=Boot to kernel, load ChromeOS VM. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 26 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/51849/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/51849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b Gerrit-Change-Number: 51849 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/sasuke: Update DPTF parameters
by Karthik Ramasubramanian (Code Review) April 5, 2021

April 5, 2021

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51970 ) Change subject: mb/google/dedede/var/sasuke: Update DPTF parameters ...................................................................... mb/google/dedede/var/sasuke: Update DPTF parameters Remove TSR2, use DPTF parameters from internal thermal team. BUG=b:183749595 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index bcc4b49..6bcde70 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -80,6 +80,45 @@ }, }" device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Vcore"" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 15000), + }" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2500 }, + [2] = { 16, 2000 }, + [3] = { 8, 1500 } + }" + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/51970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3182b96bf36c8d07299fe435a29e6b8c0b8a6927 Gerrit-Change-Number: 51970 Gerrit-PatchSet: 3 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Add audio support
by Karthik Ramasubramanian (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Dtrain Hsu, Paul Menzel. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51841 ) Change subject: mb/google/dedede/var/cret: Add audio support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fd7c374fc8214e25a28fb9ba62a9c8473d3f755 Gerrit-Change-Number: 51841 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 05 Apr 2021 15:36:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio
by Karthik Ramasubramanian (Code Review) April 5, 2021

April 5, 2021

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51335 ) Change subject: mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio ...................................................................... mb/google/dedede/var/sasuke: Configure I2C times for touchpad/audio Configure I2C rise/fall time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (< 400 kHz). Measured I2C frequency just as below after tuning: I2C0(touchpad): 385 kHz I2C4(audio): 380 kHz BUG=b:180335053 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/sasuke/overridetree.cb 1 file changed, 4 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb index 2fb1d61..bcc4b49 100644 --- a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -61,9 +61,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 66, - .fall_time_ns = 90, - .data_hold_time_ns = 350, + .rise_time_ns = 209, + .fall_time_ns = 12, }, .i2c[1] = { .speed = I2C_SPEED_FAST, @@ -76,12 +75,8 @@ }, .i2c[4] = { .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } + .rise_time_ns = 175, + .fall_time_ns = 8, }, }" device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/51335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2 Gerrit-Change-Number: 51335 Gerrit-PatchSet: 4 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Edward Doan <edoan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: Make espi_clear_decodes private
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52064 to look at the new patch set (#2). Change subject: soc/amd: Make espi_clear_decodes private ...................................................................... soc/amd: Make espi_clear_decodes private espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 3 files changed, 3 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52064/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Gerrit-Change-Number: 52064 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52056 ) Change subject: soc/amd/common/espi: Clear DNCMD_COMPLETE on completion ...................................................................... soc/amd/common/espi: Clear DNCMD_COMPLETE on completion Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index fe49fe8..c7269d0 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -519,6 +519,8 @@ return -1; } + espi_write32(ESPI_SLAVE0_INT_STS, ESPI_STATUS_DNCMD_COMPLETE); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Gerrit-Change-Number: 52056 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/espi: Reset eSPI registers to known state
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52058 ) Change subject: soc/amd/common/espi: Reset eSPI registers to known state ...................................................................... soc/amd/common/espi: Reset eSPI registers to known state This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c8309a5..fe49fe8 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -885,6 +885,11 @@ uint32_t slave_caps; const struct espi_config *cfg = espi_get_config(); + espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN); + espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); + espi_write32(ESPI_SLAVE0_INT_EN, 0); + espi_clear_status(); + /* * Boot sequence: Step 1 * Set correct initial configuration to talk to the slave: @@ -962,5 +967,8 @@ /* Enable subtractive decode if configured */ espi_setup_subtractive_decode(cfg); + espi_write32(ESPI_GLOBAL_CONTROL_1, + espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Gerrit-Change-Number: 52058 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/espi: Add missing eSPI register definitions
by Raul Rangel (Code Review) April 5, 2021

April 5, 2021

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52057 ) Change subject: soc/amd/common/espi: Add missing eSPI register definitions ...................................................................... soc/amd/common/espi: Add missing eSPI register definitions These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 45fcc6f..c8309a5 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -332,11 +332,34 @@ #define ESPI_VW_MAX_SIZE_SHIFT 13 #define ESPI_VW_MAX_SIZE_MASK (0x3f << ESPI_VW_MAX_SIZE_SHIFT) +#define ESPI_GLOBAL_CONTROL_0 0x30 +#define ESPI_WAIT_CNT_SHIFT 24 +#define ESPI_WAIT_CNT_MASK (0x3F << ESPI_WAIT_CNT_SHIFT) +#define ESPI_WDG_CNT_SHIFT 8 +#define ESPI_WDG_CNT_MASK (0xFFFF << ESPI_WDG_CNT_SHIFT) +#define ESPI_AL_IDLE_TIMER_SHIFT 4 +#define ESPI_AL_IDLE_TIMER_MASK (0x7 << ESPI_AL_IDLE_TIMER_SHIFT) +#define ESPI_AL_STOP_EN (1 << 3) +#define ESPI_PR_CLKGAT_EN (1 << 2) +#define ESPI_WAIT_CHKEN (1 << 1) +#define ESPI_WDG_EN (1 << 0) + #define ESPI_GLOBAL_CONTROL_1 0x34 +#define ESPI_RGCMD_INT_MAP_SHIFT 13 +#define ESPI_RGCMD_INT_MAP_MASK (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_RGCMD_INT_SMI (0x1F << ESPI_RGCMD_INT_MAP_SHIFT) +#define ESPI_ERR_INT_MAP_SHIFT 8 +#define ESPI_ERR_INT_MAP_MASK (0x1F << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT(irq) ((irq) << ESPI_ERR_INT_MAP_SHIFT) +#define ESPI_ERR_INT_SMI (0x1F << ESPI_ERR_INT_MAP_SHIFT) #define ESPI_SUB_DECODE_SLV_SHIFT 3 #define ESPI_SUB_DECODE_SLV_MASK (0x3 << ESPI_SUB_DECODE_SLV_SHIFT) #define ESPI_SUB_DECODE_EN (1 << 2) +#define ESPI_BUS_MASTER_EN (1 << 1) +#define ESPI_SW_RST (1 << 0) +#define ESPI_SLAVE0_INT_EN 0x6C #define ESPI_SLAVE0_INT_STS 0x70 #define ESPI_STATUS_DNCMD_COMPLETE (1 << 28) #define ESPI_STATUS_NON_FATAL_ERROR (1 << 6) -- To view, visit https://review.coreboot.org/c/coreboot/+/52057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Gerrit-Change-Number: 52057 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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