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Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52064
to look at the new patch set (#2).
Change subject: soc/amd: Make espi_clear_decodes private
......................................................................
soc/amd: Make espi_clear_decodes private
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
---
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
3 files changed, 3 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/52064/2
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Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52058 )
Change subject: soc/amd/common/espi: Reset eSPI registers to known state
......................................................................
soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 8 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index c8309a5..fe49fe8 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -885,6 +885,11 @@
uint32_t slave_caps;
const struct espi_config *cfg = espi_get_config();
+ espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN);
+ espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
+ espi_write32(ESPI_SLAVE0_INT_EN, 0);
+ espi_clear_status();
+
/*
* Boot sequence: Step 1
* Set correct initial configuration to talk to the slave:
@@ -962,5 +967,8 @@
/* Enable subtractive decode if configured */
espi_setup_subtractive_decode(cfg);
+ espi_write32(ESPI_GLOBAL_CONTROL_1,
+ espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN);
+
return 0;
}
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Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52031 )
Change subject: mb/google/dedede: add lalala variant
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/dedede/variants/lalala/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/52031/comment/5ac8acd2_80f355bb
PS2, Line 11: TBD
> Hm?
This was lifted from magalor.
https://review.coreboot.org/c/coreboot/+/52031/comment/ed4977d0_6e5690d5
PS2, Line 300: device pci 1c.7 on
> nit: I'd move this device up, so that the dev. […]
I was following magolor. I think we can reorder everything in a separate change.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52093 )
Change subject: soc/intel: Do not bridge I/O resources with base=0 to LPC
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/52093/comment/87746767_50b58aa8
PS1, Line 77:
: if (base == 0)
: return;
:
> Yeah, but the message is still far away from what the code does. […]
+1 to a different message for `base == 0`
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Change subject: soc/intel/common/block/irq: Add support for intel_write_pci0_PRT
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/irq/irq.c:
https://review.coreboot.org/c/coreboot/+/51159/comment/dedc4340_80c59c0b
PS7, Line 378: /* Map INTA->PIRQ_A, INTB->PIRQ_B, INTC->PIRQ_C, INTD->PIRQ_D */
> You are correct, this recommendation comes from the BWG guides IIRC. […]
for posterity: Sorry I misunderstood what you were getting at, we talked on IRC, I realized the error of my ways and trying a new patchset.
we also realized the old IDENTITY constraint appears to be required for PCIe RPs,
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