Change in coreboot[master]: soc/amd/common/espi: Reset eSPI registers to known state
Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52058 ) Change subject: soc/amd/common/espi: Reset eSPI registers to known state ...................................................................... soc/amd/common/espi: Reset eSPI registers to known state This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c8309a5..fe49fe8 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -885,6 +885,11 @@ uint32_t slave_caps; const struct espi_config *cfg = espi_get_config(); + espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN); + espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI); + espi_write32(ESPI_SLAVE0_INT_EN, 0); + espi_clear_status(); + /* * Boot sequence: Step 1 * Set correct initial configuration to talk to the slave: @@ -962,5 +967,8 @@ /* Enable subtractive decode if configured */ espi_setup_subtractive_decode(cfg); + espi_write32(ESPI_GLOBAL_CONTROL_1, + espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Gerrit-Change-Number: 52058 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel@chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot@felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk@gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: merged
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Raul Rangel (Code Review)