Raul Rangel submitted this change.
soc/amd/common/espi: Reset eSPI registers to known state
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index c8309a5..fe49fe8 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -885,6 +885,11 @@
uint32_t slave_caps;
const struct espi_config *cfg = espi_get_config();
+ espi_write32(ESPI_GLOBAL_CONTROL_0, ESPI_AL_STOP_EN);
+ espi_write32(ESPI_GLOBAL_CONTROL_1, ESPI_RGCMD_INT(23) | ESPI_ERR_INT_SMI);
+ espi_write32(ESPI_SLAVE0_INT_EN, 0);
+ espi_clear_status();
+
/*
* Boot sequence: Step 1
* Set correct initial configuration to talk to the slave:
@@ -962,5 +967,8 @@
/* Enable subtractive decode if configured */
espi_setup_subtractive_decode(cfg);
+ espi_write32(ESPI_GLOBAL_CONTROL_1,
+ espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN);
+
return 0;
}
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