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Change subject: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52128/comment/adc5f6a6_7055b8e1
PS2, Line 9: ASSERTION ERROR
> ASSERTION ERROR: file 'src/security/vboot/common.c', line 23
>
> Do you expect this in commit message?
Yes.
Patchset:
PS4:
The proper fix would be to have the VBOOT related part of the MRC cache driver depend on !VBOOT_START_IN_ROMSTAGE.
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Hello build bot (Jenkins), Wim Vervoorn,
I'd like you to reexamine a change. Please visit
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Change subject: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
......................................................................
mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
ASSERTION ERROR occurs when reading RW_MRC_CACHE if VBOOT is enabled.
MRC cache is loaded in early stage of ROMSTAGE. There is not enough CAR
space available for vboot workbuffer. CBMEM can not be used since memory
init is not executed.
When VBOOT is enabled, disable_saved_data is set disabling loading MRC
data.
BUG = N/A
TEST = Build and boot facebook FBG1701 with VBOOT enabled and disabled.
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93
---
M src/mainboard/facebook/fbg1701/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52128/4
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Hello build bot (Jenkins), Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52128
to look at the new patch set (#3).
Change subject: mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
......................................................................
mb/faceboot/fbg1701/romstage.c: Set disable_saved_data
ASSERTION ERROR occurs when reading RW_MRC_CACHE if VBOOT is enabled.
MRC is loaded in early stage of ROMSTAGE. There is not space available
for vboot workbuffer. CBMEM can not be used since memory init is not
executed. Available flash size is too small for _vboot2_work buffer to
start VBOOT in bootblock.
When VBOOT is enabled, disable_saved_data is set disabling loading MRC
data.
BUG = N/A
TEST = Build and boot facebook FBG1701 with VBOOT enabled and disabled.
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Change-Id: Icfedfa82e746626f35e6f1d426a4de768c594b93
---
M src/mainboard/facebook/fbg1701/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52128/3
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Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52114 )
Change subject: mb/google/guybrush: Add aux PCIe reset GPIOs to dxio descriptors
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Fagerburg, Julius Werner, Jan Dabros,
I'd like you to reexamine a change. Please visit
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Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets
......................................................................
include/assert.h: Use mock_assert() for ENV_TEST targets
Some tests have to be able to catch assertion errors.
Adding CMocka mock_assert() enables that.
Additionally fix test_imd_create_tiered_empty(),
test_full_stack() and test_incorrectly_initialized_stack()
by adding missing expect_assert_failure().
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18
---
M src/include/assert.h
M tests/lib/imd-test.c
M tests/lib/stack-test.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/51804/3
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 )
Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK
......................................................................
Patch Set 28:
(2 comments)
File src/drivers/spi/spi_flash.c:
https://review.coreboot.org/c/coreboot/+/50586/comment/85f02d66_aed9bead
PS28, Line 493: if (reg8 & 0x20){
space required before the open brace '{'
https://review.coreboot.org/c/coreboot/+/50586/comment/faadc000_07ec9100
PS28, Line 497: while (1);
trailing statements should be on next line
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