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Change subject: chromeec: Fix google_chromeec_status_check timeout
......................................................................
chromeec: Fix google_chromeec_status_check timeout
Rewrite google_chromeec_status_check to use stopwatch instead of a
delay in a while loop. In practice the while loop ends up taking
much longer than one second to timeout. Using stopwatch library will
accurately timeout after one second.
BUG=b:183524609
TEST=Build and run on guybrush
BRANCH=None
Change-Id: I363ff7453bcf81581884f92797629a6f96d42580
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M src/ec/google/chromeec/ec_lpc.c
1 file changed, 13 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/51775/6
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Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: chromeec: Fix google_chromeec_status_check timeout
......................................................................
chromeec: Fix google_chromeec_status_check timeout
Rewrite google_chromeec_status_check to use stopwatch instead of a
delay in a while loop. In practice the while loop ends up taking
much longer than one second to timeout. Using stopwatch library will
accurately timeout after one second.
BUG=b:183524609
TEST=Build and run on guybrush
BRANCH=None
Change-Id: I363ff7453bcf81581884f92797629a6f96d42580
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
---
M 3rdparty/amd_blobs
M 3rdparty/blobs
M 3rdparty/intel-microcode
M 3rdparty/qc_blobs
M src/ec/google/chromeec/ec_lpc.c
5 files changed, 17 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/51775/5
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )
Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/f0624b14_956e526e
PS1, Line 54: HIGH
> Until we handle the timings, which is not a part of this patch, this is the best way to go. […]
Wouldn't you run into issues during the bringup if you are not ensuring that the timings are met? It is going to cause random behaviors on different boards and more issues to debug. Also, the bug you raised for "handle timings" (b/184598323), does not capture any of these steps that need to be performed.
https://review.coreboot.org/c/coreboot/+/52115/comment/54c3d5ce_418bee74
PS1, Line 169: /* EN_PP3300_WLAN */
> The early gpio init is getting moved from bootblock to psp_verstage.
I think we should have two separate tables - one for verstage on PSP and other for bootblock. The PCIe related GPIOs don't really need to be configured in verstage. Those are required only before FSP-M runs and so doing it in bootblock should be perfectly fine. Also, ensures that we are able to update this in field if required.
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Change subject: tests/lib/malloc-test: Fix possible memory overrun
......................................................................
Patch Set 1: Code-Review+2
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Change subject: Makefile: export LANG LC_ALL TZ without using COREBOOT_EXPORTS
......................................................................
Patch Set 4: Code-Review+2
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Change subject: util/genbuild_h: add support to print SOURCE_DATE_EPOCH
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Not _too_ happy about adding an option for that here (which will encourage adding all kinds of other options, yuck).
We sometimes parse stuff out of build.h, eg in src/arch/arm64/Makefile.inc:
BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell sed -n 's/^.define COREBOOT_BUILD\>.*"\(.*\)".*/\1/p' $(obj)/build.h)"'
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Change subject: lint: checkpatch: Add SUSPICIOUS_CODE_INDENT test
......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Patchset:
PS2:
There's compiler tooling for that since gcc6 (-Wmisleading-indentation) and while it's also just heuristics, at least it's more widely used heuristics than this, so let's go that route?
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Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets
......................................................................
Patch Set 3: Code-Review+2
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51985 )
Change subject: Revert "mb/google/guybrush: Disable GFX"
......................................................................
Revert "mb/google/guybrush: Disable GFX"
This reverts commit 52e61945588bc327844acc4658426861d63ad189.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin Roth <martinroth(a)google.com>
---
M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
1 file changed, 1 insertion(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 7ca9175..f5f9018 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -48,8 +48,7 @@
device ref gpp_bridge_3 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
- # b/183971103 - We can't enable GFX because it locks up the OS
- device ref gfx off end # Internal GPU (GFX)
+ device ref gfx on end # Internal GPU (GFX)
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
device ref xhci_0_root_hub on
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