coreboot-gerrit April 2021

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Change in coreboot[master]: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jason Glenesk, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51932 ) Change subject: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f Gerrit-Change-Number: 51932 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:41:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package
by Felix Held (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51932 to look at the new patch set (#2). Change subject: soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package ...................................................................... soc/amd/picasso/acpi: fix domain argument of acpigen_write_CSD_package Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f --- M src/soc/amd/picasso/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/51932/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50e88ac946b9d8797571f9e3d4b325db760e423f Gerrit-Change-Number: 51932 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Selma Bensaid (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Maulik V Vaghela, Subrata Banik, Bernardo Perez Priego, Thejaswani Putta, Patrick Rudolph. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52140 ) Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:39:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU
by Paul Menzel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Li1 Feng, John Zhao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52137 ) Change subject: mb/google/volteer: Add EC_HOST_EVENT_PD_MCU ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52137/comment/4f2cfe7c_039d7f02 PS2, Line 13: PD DP? -- To view, visit https://review.coreboot.org/c/coreboot/+/52137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44e4075f42e9a95d26fe766489630dac0bc61b05 Gerrit-Change-Number: 52137 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:33:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Anil Kumar K (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Bora Guvendik, Cliff Huang, Maulik V Vaghela, Selma Bensaid, Subrata Banik, Bernardo Perez Priego, Anil Kumar K, Thejaswani Putta, Patrick Rudolph. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52140 ) Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:25:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable ALC711 over SNDW0
by Selma Bensaid (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Varshit B Pandya, SRIDHAR SIRICILLA, Rizwan Qureshi, Sridhar Siricilla. Selma Bensaid has uploaded a new patch set (#23) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/50022 ) Change subject: mb/intel/adlrvp: Enable ALC711 over SNDW0 ...................................................................... mb/intel/adlrvp: Enable ALC711 over SNDW0 The patch enables ALC711 over SNDW0. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa --- M src/mainboard/intel/adlrvp/gpio_m.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/50022/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/50022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa Gerrit-Change-Number: 50022 Gerrit-PatchSet: 23 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.corp-partner.google.com> Gerrit-CC: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing
by Anil Kumar K (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Anil Kumar K. Hello Anil Kumar K, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52140 to review the following change. Change subject: soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing ...................................................................... soc/intel/alderlake: Enable NPK/VISA for PCH and CPU tracing - Enable Trace Hub - Set debugger mode to Host debugger Branch=None Test=Build and boot on ADL-M RVP. Execute BVT TAST test cases Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree_m.cb M src/soc/intel/alderlake/romstage/fsp_params.c 3 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/52140/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index c1c4586..8169f3b 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -18,6 +18,7 @@ select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_DEBUG_CONSENT config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON @@ -61,6 +62,22 @@ string default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" +config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT + int "Debug Consent for ADL" + # USB DBC is more common for developers so make this default to 3 if + # SOC_INTEL_DEBUG_CONSENT=y + default 7 if SOC_INTEL_DEBUG_CONSENT + default 0 + help + This is to control debug interface on SOC. + Setting non-zero value will allow to use DBC or DCI to debug SOC. + PlatformDebugConsent in FspmUpd.h has the details. + + Desired platform debug type are + 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), + 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), + 6:Enable (2-wire DCI OOB), 7:Manual + config DIMM_SPD_SIZE int default 512 diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 7c69163..2995670 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -260,6 +260,6 @@ device pci 1f.4 on end # SMBus device pci 1f.5 on end # SPI device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH + device pci 1f.7 on end # TH end end diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 3852467..04ccf94 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -126,6 +126,16 @@ /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; + /* Disable DCI DBC mode */ + m_cfg->DciDbcMode = 0; + + /* Disable platform debugger support */ + m_cfg->DciUsb3TypecUfpDbg = 0; + + /* Set trace debug mode to Host Debugger Mode */ + m_cfg->PchTraceHubMode = 2; + m_cfg->CpuTraceHubMode = 2; + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ dev = pcidev_path_on_root(PCH_DEVFN_HDA); m_cfg->PchHdaEnable = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/52140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16086e3ce92c5d54fbeae9444c0608b31c1ad01e Gerrit-Change-Number: 52140 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/fsp/cezanne: add platform_descriptors.h
by Matt Papageorge (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Justin Frodsham, Marshall Dawson, Felix Held. Matt Papageorge has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51197 ) Change subject: vc/amd/fsp/cezanne: add platform_descriptors.h ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Gerrit-Change-Number: 51197 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:21:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: HAOUAS Elyes. Angel Pons has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0"
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Michael Niewöhner, Alexander Couzens, HAOUAS Elyes. Hello build bot (Jenkins), Michael Niewöhner, Alexander Couzens, HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/51986 to review the following change. Change subject: Revert "src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0" ...................................................................... Revert "src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0" This reverts commit 81d55cf6d62ac710df030fc02dd3ca00f3d80405. Reason for revert: No reason given, not known to be tested, and has a mistake that most likely introduced a recent regression, as reported in mailing list thread `problem after "convert to ASL 2.0"`. Change-Id: Ifffe0730fb6f204abf8b5fe99f4e37015bb8d5b7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/lenovo/h8/acpi/battery.asl 1 file changed, 41 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/51986/1 diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index d5e8c12..42b91b9 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -80,7 +80,7 @@ */ Method(BPAG, 1, NotSerialized) { - PAGE = Arg0 + Store(Arg0, PAGE) #ifdef BATTERY_PAGE_DELAY_MS Sleep(BATTERY_PAGE_DELAY_MS) #endif @@ -94,32 +94,32 @@ Method(BSTA, 4, NotSerialized) { Acquire(ECLK, 0xffff) - Local0 = 0 - ^BPAG(Arg0 | 1) - Local1 = BAMA + Store(0, Local0) + ^BPAG(Or(1, Arg0)) + Store(BAMA, Local1) ^BPAG(Arg0) /* Battery dynamic information */ /* * Present rate is a 16bit signed int, positive while charging * and negative while discharging. */ - Local2 = BAPR + Store(BAPR, Local2) If (Arg2) // Charging { - Local0 |= 2 + Or(2, Local0, Local0) } Else { If (Arg3) // Discharging { - Local0 |= 1 + Or(1, Local0, Local0) // Negate present rate - Local2 -= 0x10000 + Subtract(0x10000, Local2, Local2) } Else // Full battery, force to 0 { - Local2 = 0 + Store(0, Local2) } } @@ -127,21 +127,21 @@ * The present rate value must be positive now, if it is not we have an * EC bug or inconsistency and force the value to 0. */ - If (Local2 >= 0x8000) { - Local2 = 0 + If (LGreaterEqual (Local2, 0x8000)) { + Store(0, Local2) } - Arg1 [0] = Local0 + Store(Local0, Index(Arg1, 0x00)) if (Local1) { - Arg1 [2] = BARC * 10 - Local2 *= BAVO - Arg1 [1] = Local2 / 1000 + Multiply (BARC, 10, Index(Arg1, 2)) + Multiply (Local2, BAVO, Local2) + Divide (Local2, 1000, , Index(Arg1, 1)) } else { - Arg1 [2] = BARC - Arg1 [1] = Local2 + Store(BARC, Index(Arg1, 2)) + Store(Local2, Index(Arg1, 1)) } - Arg1 [3] = BAVO + Store(BAVO, Index(Arg1, 3)) Release(ECLK) Return (Arg1) } @@ -150,45 +150,43 @@ { Acquire(ECLK, 0xffff) ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ - Arg0 [0] = BAMA ^ 1 - Local0 = BAMA + Xor(BAMA, 1, Index(Arg0, 0)) + Store(BAMA, Local0) ^BPAG(Arg1) - Local2 = BAFC - ^BPAG(Arg1 | 2) - Local1 = BADC + Store(BAFC, Local2) + ^BPAG(Or(2, Arg1)) + Store(BADC, Local1) if (Local0) { - Local1 *= 10 - Local2 *= 10 + Multiply (Local1, 10, Local1) + Multiply (Local2, 10, Local2) } - Arg0 [1] = Local1 // Design Capacity - Arg0 [2] = Local2 // Last full charge capacity - Arg0 [4] = BADV // Design Voltage - Local0 = Local2 % 20 // FIXME: Local0 not used - Arg0 [5] = Local2 / 20 // Warning capacity + Store(Local1, Index(Arg0, 1)) // Design Capacity + Store(Local2, Index(Arg0, 2)) // Last full charge capacity + Store(BADV, Index(Arg0, 4)) // Design Voltage + Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity - Local0 = BASN + Store (BASN, Local0) Name (SERN, Buffer (0x06) { " " }) - Local1 = 4 + Store (4, Local1) While (Local0) { - Local2 = Local0 % 10 - Local0 /= 10 - SERN [Local1] = Local2 + 48 - Local1-- + Divide (Local0, 0x0A, Local2, Local0) + Add (Local2, 48, Index (SERN, Local1)) + Decrement (Local1) } - Arg0 [10] = SERN // Serial Number + Store (SERN, Index (Arg0, 10)) // Serial Number ^BPAG(Or(4, Arg1)) Name (TYPE, Buffer() { 0, 0, 0, 0, 0 }) - TYPE = BATY - Arg0 [11] = TYPE // Battery type - ^BPAG(Arg1 | 5) - Arg0 [12] = BAOE // OEM information - ^BPAG(Arg1 | 6) - Arg0 [9] = BANA // Model number + Store(BATY, TYPE) + Store(TYPE, Index (Arg0, 11)) // Battery type + ^BPAG(Or(5, Arg1)) + Store(BAOE, Index (Arg0, 12)) // OEM information + ^BPAG(Or(6, Arg1)) + Store(BANA, Index (Arg0, 9)) // Model number Release(ECLK) Return (Arg0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/51986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifffe0730fb6f204abf8b5fe99f4e37015bb8d5b7 Gerrit-Change-Number: 51986 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021