coreboot-gerrit April 2021

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Change in coreboot[master]: alderlake: enable DPTF functionality for ADL-RVP board
by Sumeet R Pawnikar (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52020 to look at the new patch set (#2). Change subject: alderlake: enable DPTF functionality for ADL-RVP board ...................................................................... alderlake: enable DPTF functionality for ADL-RVP board Enable DPTF functionality for alderlake based ADL-RVP board BRANCH=None BUG=None TEST=Built for adlrvp and tested on adlrvp board Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/drivers/intel/dptf/dptf.c M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree.cb 3 files changed, 110 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/52020/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Gerrit-Change-Number: 52020 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] alderlake: enable DPTF functionality for ADL-RVP board
by Sumeet R Pawnikar (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52020 ) Change subject: [WIP] alderlake: enable DPTF functionality for ADL-RVP board ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/52020/comment/8918649b_82aa052f PS1, Line 28: /* Below are ACPI IDs for Alder Lake SoC */ > Need to check how we can add different new SoCs ACPI IDs like Tiger Lake, Alder Lake, etc. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Gerrit-Change-Number: 52020 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:16:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 3: (1 comment) File src/ec/lenovo/h8/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/50317/comment/82bc4549_b8688c70 PS3, Line 169: Local0 = Local2 % 20 // FIXME: Local0 not used So, why is this kept? -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 06 Apr 2021 19:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Anil Kumar K (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Meera Ravindranath. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... Patch Set 7: (1 comment) File src/mainboard/intel/adlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/51408/comment/cd1cacc0_70e923f4 PS7, Line 49: Alder Lake Client Platform Does this change affect mosys or cros_config. I think this config is reported as FRID and it is used by mosys to do platform matching . Does mosys platform name and cros_config / name work OK with this change ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 18:58:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Nico Huber (Code Review) 06 Apr '21

06 Apr '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... soc/intel/common: Prevent SMI storm when setting SPI WPD bit From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 31 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 58e3ca2..a3481c6 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -387,6 +387,20 @@ fast_spi_init(); } +/* Clear SPI Synchronous SMI status bit and return its value. */ +bool fast_spi_clear_sync_smi_status(void) +{ + const uint32_t bios_cntl = pci_read_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL); + const bool smi_asserted = bios_cntl & SPI_BIOS_CONTROL_SYNC_SS; + /* + * Do not unconditionally write 1 to clear SYNC_SS. Hardware could set + * SYNC_SS here (after we read but before we write SPI_BIOS_CONTROL), + * and the event would be lost when unconditionally clearing SYNC_SS. + */ + pci_write_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL, bios_cntl); + return smi_asserted; +} + /* Read SPI Write Protect disable status. */ bool fast_spi_wpd_status(void) { diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 945feb0..4f79b75 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -17,6 +17,7 @@ #define SPI_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) #define SPI_BIOS_CONTROL_EISS (1 << 5) #define SPI_BIOS_CONTROL_BILD (1 << 7) +#define SPI_BIOS_CONTROL_SYNC_SS (1 << 8) #define SPI_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27) #define SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28) #define SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff)) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 3ba240b..d044256 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -65,6 +65,10 @@ */ extern const struct spi_ctrlr fast_spi_flash_ctrlr; /* + * Clear SPI Synchronous SMI status bit and return its value. + */ +bool fast_spi_clear_sync_smi_status(void); +/* * Read SPI Write protect disable bit. */ bool fast_spi_wpd_status(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index a15bc7c..2c3364a 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -384,6 +384,18 @@ { uint32_t tco_sts = pmc_clear_tco_status(); + /* + * SPI synchronous SMIs are TCO SMIs, but they do not have a status + * bit in the TCO_STS register. Furthermore, the TCO_STS bit in the + * SMI_STS register is continually set until the SMI handler clears + * the SPI synchronous SMI status bit in the SPI controller. To not + * risk missing any other TCO SMIs, do not clear the TCO_STS bit in + * this SMI handler invocation. If the TCO_STS bit remains set when + * returning from SMM, another SMI immediately happens which clears + * the TCO_STS bit and handles any pending events. + */ + fast_spi_clear_sync_smi_status(); + /* Any TCO event? */ if (!tco_sts) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 16 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 3: (1 comment) File src/ec/lenovo/h8/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/50317/comment/59e9a811_217e7282 PS3, Line 118: Local2 -= 0x10000 This looks wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 06 Apr 2021 18:55:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Nico Huber, Matt DeVillier, Tim Wawrzynczak, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50754/comment/cdfa9e69_0338ce7d PS14, Line 21: It is thus necessary to clear the SMI_STS : register again > This looks outdated. Done https://review.coreboot.org/c/coreboot/+/50754/comment/2f52f5d4_0ff81dce PS14, Line 39: out-of-tree This was also outdated. -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 15 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 18:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Angel Pons (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Patrick Rudolph, Matt DeVillier, Benjamin Doron, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50754 to look at the new patch set (#15). Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... soc/intel/common: Prevent SMI storm when setting SPI WPD bit From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 15 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
by Nico Huber (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Matt DeVillier, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50754 ) Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit ...................................................................... Patch Set 14: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50754/comment/a3f4f9fe_357f6c14 PS14, Line 21: It is thus necessary to clear the SMI_STS : register again This looks outdated. -- To view, visit https://review.coreboot.org/c/coreboot/+/50754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Gerrit-Change-Number: 50754 Gerrit-PatchSet: 14 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 18:46:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Add support to handle pen detection
by Karthik Ramasubramanian (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: David Wu, Furquan Shaikh, Henry Sun, Evan Green, Justin TerAvest. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51709 ) Change subject: mb/google/dedede/var/metaknight: Add support to handle pen detection ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a Gerrit-Change-Number: 51709 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Evan Green <evgreen(a)chromium.org> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 18:17:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2021