coreboot-gerrit April 2021

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Change in coreboot[master]: Revert "mb/google/guybrush: Disable GFX"
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth, Mathew King, Felix Held. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Mathew King, Felix Held, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/51985 to review the following change. Change subject: Revert "mb/google/guybrush: Disable GFX" ...................................................................... Revert "mb/google/guybrush: Disable GFX" This reverts commit 52e61945588bc327844acc4658426861d63ad189. Reason for revert: Graphics actually works now. I should have abandoned this CL. Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/51985/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 7ca9175..f5f9018 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -48,8 +48,7 @@ device ref gpp_bridge_3 on end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A - # b/183971103 - We can't enable GFX because it locks up the OS - device ref gfx off end # Internal GPU (GFX) + device ref gfx on end # Internal GPU (GFX) device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi device ref xhci_0_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/51985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83aac3a2c616bb434706f23e36549760bc764080 Gerrit-Change-Number: 51985 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52115 to look at the new patch set (#2). Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... mb/google/guybrush: PCIe GPIOs - enable enables, disable resets To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 16 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52115/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARING
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, EricR Lai, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52125 ) Change subject: mb/google/mancomb: Enable DISABLE_SPI_FLASH_ROM_SHARING ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d28c2335b095a77285dcb261a0dffe96d129c46 Gerrit-Change-Number: 52125 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:23:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable early EC Software Sync
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Paul Menzel, EricR Lai, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52124 ) Change subject: mb/google/mancomb: Enable early EC Software Sync ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9768feaadf2423acd50a71e9a2310b4ab2d1a2a8 Gerrit-Change-Number: 52124 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:23:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Add eSPI GPIO back to init table
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Mathew King, EricR Lai. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52123 ) Change subject: mb/google/mancomb: Add eSPI GPIO back to init table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc Gerrit-Change-Number: 52123 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:22:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Configure UART0 gpio in early stage
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Mathew King, EricR Lai. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52122 ) Change subject: mb/google/mancomb: Configure UART0 gpio in early stage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4ec1556ac7136c454eb025ff99aafbf49b8982 Gerrit-Change-Number: 52122 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:22:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Enable PCIe devices in devicetree
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth, Mathew King, EricR Lai. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52118 ) Change subject: mb/google/mancomb: Enable PCIe devices in devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6c20b32ddafe415132ce70abf5381ff3aad13f7 Gerrit-Change-Number: 52118 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:15:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Add initial fch irq routing
by Raul Rangel (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth, Mathew King, EricR Lai. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52117 ) Change subject: mb/google/mancomb: Add initial fch irq routing ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850a3ecc8776593d97f4162e812a39991caa30ef Gerrit-Change-Number: 52117 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:15:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Martin Roth (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Furquan Shaikh. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 ) Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/52115/comment/be0779f7_8abd49ff PS1, Line 54: HIGH > But why? In my opinion that is not the right direction to take. […] Until we handle the timings, which is not a part of this patch, this is the best way to go. The chips need to be powered for a while before taking them out of reset. With the current initialization steps, that's not possible. When we do handle the timings, which can be soon, but not today, this can be addressed. https://review.coreboot.org/c/coreboot/+/52115/comment/0da80bf7_bcb712d1 PS1, Line 169: /* EN_PP3300_WLAN */ > Why is this dependent on PSP verstage? The early gpio init is getting moved from bootblock to psp_verstage. So any timings we establish right now will be changed when that move happens. Because of the move of the PCIe training from FSP-M on Picasso to FSP-S on Cezanne, I suspect we're going to need that additional time anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 06 Apr 2021 15:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Enable RTD3 for SD card
by Rizwan Qureshi (Code Review) 06 Apr '21

06 Apr '21

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52134 ) Change subject: mb/intel/shadowmountain: Enable RTD3 for SD card ...................................................................... mb/intel/shadowmountain: Enable RTD3 for SD card Enable the PCIe RTD3 driver for the PCIe attached SD card interface and provide the enable/reset GPIOs. TEST=Tested on shadowmountai platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52134/1 diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 8b31784..ffb2065 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -304,7 +304,13 @@ device pci 1c.4 on end # RP5 device pci 1c.5 off end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 on end # RP8 + device pci 1c.7 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + end + end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 off end # RP11 -- To view, visit https://review.coreboot.org/c/coreboot/+/52134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Gerrit-Change-Number: 52134 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021