Attention is currently required from: Furquan Shaikh.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52115 )
Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52115/comment/be0779f7_8abd49ff
PS1, Line 54: HIGH
> But why? In my opinion that is not the right direction to take. […]
Until we handle the timings, which is not a part of this patch, this is the best way to go. The chips need to be powered for a while before taking them out of reset. With the current initialization steps, that's not possible.
When we do handle the timings, which can be soon, but not today, this can be addressed.
https://review.coreboot.org/c/coreboot/+/52115/comment/0da80bf7_bcb712d1
PS1, Line 169: /* EN_PP3300_WLAN */
> Why is this dependent on PSP verstage?
The early gpio init is getting moved from bootblock to psp_verstage. So any timings we establish right now will be changed when that move happens. Because of the move of the PCIe training from FSP-M on Picasso to FSP-S on Cezanne, I suspect we're going to need that additional time anyway.
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Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52134 )
Change subject: mb/intel/shadowmountain: Enable RTD3 for SD card
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mb/intel/shadowmountain: Enable RTD3 for SD card
Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and provide the enable/reset GPIOs.
TEST=Tested on shadowmountai platform to ensure the system can enter the
S0i3.2 substate and suspend/resume is stable
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52134/1
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 8b31784..ffb2065 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -304,7 +304,13 @@
device pci 1c.4 on end # RP5
device pci 1c.5 off end # RP6
device pci 1c.6 off end # RP7
- device pci 1c.7 on end # RP8
+ device pci 1c.7 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
+ register "srcclk_pin" = "3"
+ end
+ end # RP8
device pci 1d.0 on end # RP9
device pci 1d.1 off end # RP10
device pci 1d.2 off end # RP11
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